Multi-pin Nets Research Articles

Fuzzy-Clustering-Based Circular Topological Via Minimization in PCB Designs

It is necessary for reliability and yield to minimize the number of used vias on nets in printed circuit board (PCB) designs. To our knowledge, the proposed fuzzy-clustering-based algorithm is the first work for a general routing region with multiple-pin nets in k -layer circular topological via minimization ( k -CTVM). In this article, given the topological connections in a set of routing nets and a set of k available layers in a routing plane, first, all the multipin nets can be transformed into a set of two-pin nets by introducing a set of preassigned vias onto the branch points on multipin nets and a conflict graph can be constructed for a final set of two-pin nets. Furthermore, the probabilistic similarity between two connected vertices using the same color can be computed for the constrained vertex-coloring problem with k colors in a conflict graph. Next, based on the definition of the clustering distance between two connected vertices in a conflict graph, fuzzy graph clustering can be developed to obtain a fuzzy matrix on k clusters. Finally, all the given nets can be assigned onto the k available layers by introducing a set of necessary vias on two-pin nets and eliminating the unnecessary preassigned vias on multipin nets. Compared with the combination of Cong's algorithm and an iterative net postassignment, NetInsertion1 , in the k -CTVM problem, the experimental results show that our proposed fuzzy-clustering- based algorithm can use less CPU time to reduce 57.3% of the number of the total used vias for eight tested PCB designs. Compared with the combination of Yan's algorithm and an iterative net postassignment, NetInsertion2 , in the k -CTVM problem, the experimental results show that our proposed fuzzy-clustering-based algorithm can reduce 34.0% of the number of the total used vias for eight tested PCB designs.

SAT based solutions for detailed routing of island style FPGA architectures

Detailed routing solutions for island style FPGA architectures using Boolean satisfiability (SAT) based formulations have been proposed in this paper. Due to decreasing size of ICs and hence, the increasing complexity of the routing resource constraints, routing has been a big challenge in electronic design automation field. Our proposed techniques work on multi-pin net routing where all nets are considered for routing in their intact form whereas, most of the existing routing solutions decompose multi-pin nets into two-pin nets for detailed routing to ease the problem. However this approach, apart from increasing the number of nets in the circuits, may also introduce pin doglegging which, when not permitted by the architecture of FPGA, would require extra constraints to eliminate. Many detailed routers adopt sequential detailed routing approaches which are vulnerable to the net ordering problem which may cause a routable circuit to be erroneously classified as unroutable. Our proposed techniques avoid these pitfalls by keeping the multi-pin nets intact and solve all nets simultaneously using SAT. The SAT-based multi-pin net dogleg-free formulations presented here achieve significant improvement over existing SAT-based solutions with respect to the number of variables and clauses used, thereby achieving greater scalability and also display comparable and sometimes better routability results on benchmark circuits when compared with other detailed routing solutions. Detailed routing is also significantly affected by the architecture of the switching blocks. This paper proposes SAT-based formulation for three different switch box architectures i.e. Subset, Wilton, and Universal switches. Our experiments clearly demonstrate how routing solutions for a circuit can differ significantly for different types of switch boxes.

Obstacle-avoiding rectilinear Steiner tree construction in sequential and parallel approach

The Rectilinear Steiner Minimum Tree (RSMT) problem is a fundamental one in VLSI physical design. In this paper, we present a maze routing based heuristics to solve the obstacle-avoiding RSMT (OARSMT) problem. Our approach can handle multi-pin nets in good quality and reasonable running time. We also present an implementation of the heuristics in parallel approach with the aid of graphic processing units (GPU). The parallel algorithm is implemented by using CUDA and has been tested on a NVIDIA graphic card. Our experimental results show that our parallel algorithm has promising speedups over our sequential approach. This work demonstrates that we can apply a parallel algorithm to solve the OARSMT problem with the aid of GPU.

Accurate estimation of global buffer delay within a floorplan

Closed-form expressions for buffered interconnect delay approximation have been around for some time. However, previous approaches assume that buffers are free to be placed anywhere. In practice, designs frequently have large blocks that make the ideal buffer-insertion solution unrealizable. The theory of Otten (ACM/IEEE Intl. Symp. Physical Design, p. 104, 1998) is extended to show how one can model the blocks into a simple delay-estimation technique that applies to both two-pin and multipin nets. Even though the formula uses one buffer type, it shows remarkable accuracy in predicting delay when compared to an optimal realizable buffer-insertion solution. Potential applications include wire planning, timing analysis during floorplanning, or global routing. The authors' experiments show that their approach accurately predicts delay when compared to constructing a realizable buffer insertion with multiple buffer types.

A fast algorithm for optimal buffer insertion

The classic buffer insertion algorithm of van Ginneken has time and space complexity O(n/sup 2/), where n is the number of possible buffer positions. For more than a decade, van Ginneken's algorithm has been the foundation of buffer insertion. In this paper, we present a new algorithm that computes the same optimal buffer insertion, but runs much faster. For 2-pin nets, our time complexity is O(nlogn) and space complexity is O(n). For multipin nets, our time complexity is O(nlog/sup 2/n) and space complexity is O(nlogn). The speedup is achieved by four novel techniques: predictive pruning, candidate tree, fast redundancy check, and fast merging. On industrial test cases, the new algorithms is 2-80 times faster than van Ginneken's algorithm and uses 1/4-1/500 of the memory. Since van Ginneken's algorithm and its variations are used by most existing algorithms on buffer insertion and buffer sizing, our new algorithm significantly improves the performance of all these algorithms. The predictive pruning technique has been applied to buffer cost minimization (Shi et al., 2004), and significantly improved the running time.

General models and a reduction design technique for FPGA switch box designs

An FPGA switch box is said to be hyper-universal if it is detailed-routable for any set of multipin nets specifying a routing requirement over the switch box. Comparing with the known "universal switch modules", where only 2-pin nets are considered, the hyper-universal switch box model is more general and powerful. This paper studies the generic problem and proposes a systematic designing methodology for hyper-universal (k, W)-switch boxes, where k is the number of sides and W is the number of terminals on each side. We formulate this hyper-universal (k, W)-switch box design problem as a k-parfite graph design problem and propose an efficient reduction design technique. Applying this technique, we can design hyper-universal (k, W)-switch boxes with low O(W) switches for any fixed k. For illustration, we provide optimum hyper-universal (2, W) and (3, W)-switch boxes and a hyper-universal (4, W)-switch box with switch number quite close to the lower bound 6W, which is used in a well-known commercial design without hyper-universal routability. We also conclude that the proposed reduction method can yield an efficient detailed routing algorithm for any given routing requirement as well.

Planar topological routing

We develop a simple linear time algorithm to determine if a collection of two-pin nets can be routed, topologically, in a plane (i.e., single layer). Experiments indicate that this algorithm is faster than the linear time algorithm of Marek-Sadowska and Tarng. Topological routability testing of a collection of multipin nets is shown to be equivalent to planarity testing, and a simple linear time algorithm is developed for the case when the collection of modules remains connected following the deletion of all nets with more than two pins.