Multilevel Voltage Source Inverter Research Articles

Design and validation of a multilevel voltage source inverter based on modular H-bridge cells

Generation, power conversion and subsequent integration of renewable energy generation systems, such as solar photovoltaic or wind, require an efficient power conversion system that can provide sufficient quality energy according to technical standards (e.g. IEEE 519–2022). In this context, this paper focuses on the analysis, design and experimental validation of a multilevel voltage source inverter (VSI) scheme based on H-bridge cells with a modular and scalable structure for its application in power electronic converter circuits. The designed and assembled experimental setup is a versatile platform for testing experimentally varied control strategies and power converter configurations, such as the number of levels (3, 5, 7 levels) and phases (single-phase or three-phase). Therefore, the hardware design process proposed for the H-bridge cell and the measurement and conditioning circuits for voltage and current signals necessary for implementing the control algorithms are explained in detail. Moreover, a quantitative analysis of the operation of the design was carried out from measurements made with the experimental platform to verify its correct operation. Among the analysed parameters, the generated harmonics level stands out, quantified by calculating the total harmonic distortion and the mean square error between the reference signals and the measured values.

Investigation of Single-Phase, Single Voltage Source Multilevel Inverter with Voltage Boosting Gain Based on Different Sinusoidal Pulse Width Modulation Approach

Investigation of Single-Phase, Single Voltage Source Multilevel Inverter with Voltage Boosting Gain Based on Different Sinusoidal Pulse Width Modulation Approach

Comparative analysis of multilevel voltage source inverters used to supply a five-phase Permanent Magnet Synchronous Motor

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An optimized reduced switch load dependent 9-level VSI for high performance vector controlled PMSM drive

This paper presents the vector control of permanent magnet synchronous motor with load dependent voltage source multi-level inverter. The proposed voltage source multi-level inverter produces 9-level three phase balanced output voltage. The inverter switches are triggered in such a way that it can produce 5-level, 7-level, 9-level output voltage. The level of generated output voltage depends on the loading condition of inverter. The proposed inverter is connected to the permanent magnet synchronous motor for improved performance of drive. The concept of vector control has been used for decoupled control of torque and flux components of current; hence the permanent magnet synchronous motor is controlled like separately excited DC motor. The proposed work had been developed in MATLAB/SIMULINK environment and the performance had been investigated with change in load and speed. To show the effectiveness of proposed inverter FFT analysis of stator current, develop output voltage is done and THD is less than 5%. The ripple in electromagnetic torque had been reduced compared to existing methods. Hence it has been observed that overall performance of drive is enhanced.

Nine-Level Nine-Switch Common-Ground Switched-Capacitor Inverter Suitable for High-Frequency AC-Microgrid Applications

Voltage source multilevel inverters with reduced leakage current, single-stage voltage step-up feature, compact design, and an efficient performance are a promising technology for high-frequency ac (HFac) microgrids feeding through renewable energy sources. This article proposes a novel single-source common-grounded (CG) step-up nine-level (9L) inverter, which can be applied in HFac microgrid applications. The proposed CG-based boost inverter is comprised of only nine switches (9S) and three self-balanced capacitors. Using the switched-capacitor (SC) technique, a double voltage boosting feature within a single power processing stage is achieved, while the leakage current concern is eliminated due to a CG-based configuration between the input dc source and the null of the grid. With the help of an <i>LC</i> input filter, the input current profile is free from large discontinuous inrush spikes. The working principles of the proposed 9L9S-CGSC inverter are discussed in this article. The modulation and closed-loop control strategy, as well as a comparative study, are presented. Finally, the open and closed-loop grid-tied performances of the proposed topology are evaluated by both simulation and experimental results obtained from a 1.2-kW laboratory-built prototype.

Single-Phase Voltage Source Multi-Level Inverter Hysteresis SVPWM Reconfigurable Fault-Tolerant Control Method

A hysteresis space vector pulse width modulation (SVPWM) reconfigurable fault-tolerant method for single-phase voltage source multi-level inverter with current tracking is proposed. Firstly, the influence of single switch open circuit fault and double switches open circuit fault on the voltage vector of the inverter is analyzed, and on this basis, the equivalent replacement of the voltage vector is obtained by using the topology reconstruction of the inverter, and the redundant voltage vectors with overlapping positions are preferred for equivalent replacement. If there are no coincident non-fault vectors, the other non-fault vectors with the closest position and effect are selected. The fault-tolerant method does not need the switching operation between the main power switching device and spare power switching device of the inverter, and can directly control the on–off process of the inverter reconfiguration unit through the driving signal of insulated gate bipolar translator (IGBT), which is simple and stable. Under the conditions of single switch open circuit and most double switches open circuit, the output current of the inverter can accurately track the reference current.

Asymmetrical eleven‐level inverter topology with reduced power semiconductor switches, total standing voltage and cost factor

Voltage source multilevel inverters (MLI) is widely utilized in medium and high-power applications due to their advantages. Here, an 11-level, asymmetrical multilevel inverter topology is proposed. The topology utilizes four unidirectional switches, three bidirectional switches along with two dc sources. The proposed configuration of switches and the concept of the dc-link capacitor is utilized to generate eleven level output voltage. The reduced number of components such as power switches and DC sources, lower control complexity due to capacitors' self-balancing nature, and low total standing voltage (TSV) are the critical features of the proposed topology. Moreover, a reliability assessment of the topology shows that the topology has a high mean time to fault (MTTF), which makes it robust and reliable. Matlab/Simulink environment is used to develop a simulation model of the proposed topology, while PLECS is used for the thermal modelling and analysis of the converter. A prototype is developed and tested in the laboratory to validate the performance for different loading conditions. The proposed topology can be cascaded to produce the ‘n’ number of levels. The critical comparison of the proposed topology shows that the proposed circuit has advantages over other compared topologies.

Selective Harmonic Elimination of a Multilevel Voltage Source Inverter Using Whale Optimization Algorithm

In this paper, the whale optimization algorithm is proposed for harmonics elimination in a cascaded multilevel inverter. In selective harmonic elimination pulse width modulation, the selected low-order harmonics are eliminated by solving nonlinear equations, while the fundamental of output waveform is adjusted to a desired value. In this paper, whale optimization algorithm is applied to a 7-level cascaded H-bridge inverter to solve the equations. Also, it was validated by experimental results, since this algorithm has an ability to search in entire solution space, the probability of catching a global best solution is very high. This method has higher accuracy and probability of convergence than the genetic algorithm. The optimization and comparison of whale optimization algorithm and genetic algorithm have been done in MATLAB software. A 1 kW prototype of this converter is built and the results are presented. The effectiveness and the theoretical analysis of this method are verified through both simulation and experimental results

Asymmetrical 17-Level Inverter Topology With Reduced Total Standing Voltage and Device Count

Voltage source Multilevel Inverters (MLIs) are vital components for medium voltage and high-power applications due to their advantages like modularity and better power quality. However, the number of components used is significant. In this paper, an improved asymmetrical multilevel inverter topology is proposed producing 17-levels output voltage utilizing two dc sources. The circuit is developed to reduce the number of isolated dc-sources used without reducing output levels. The circuit utilizes six two-quadrant switches, three four-quadrant switches and four capacitors. The capacitors are self-balancing and do not require extra attention, i.e. the control system is simple for the proposed MLI. Detailed analysis of the topology under linear and non-linear loading conditions is carried out. Comparison with other similar topologies shows that the proposed topology is superior in device count, power quality, Total Standing Voltage (TSV), and cost factor. The performance of the topology is validated for different load conditions through MATLAB/Simulink environment and the prototype developed in the laboratory. Furthermore, thermal analysis of the circuit is done, and the losses are calculated via PLECS software. The topology offers a total harmonic distortion (THD) of 4.79% in the output voltage, with all the lower order harmonics being less than 5% complying with the IEEE standards.

Combined use of the nearest vector selecting technique and low-frequency quarter-wave symmetric space vector PWM in control of three-phase multilevel voltage source inverter

The paper offers the problem’s solution of the three-phase multilevel voltage source inverter (MLVSI) control with low dynamic losses in power semiconductor switches. The proposed technique is based on a single approach that operates with values of the integer and fractional parts of the relative values of the reference delta voltages, and it allows combining the use of the space-vector control, choosing the nearest vector (SVC), with the low-frequency space-vector pulse-width modulation with the quarter-wave symmetry of the output voltages (QWS-SVPWM). Depending on the impedance kind of a generalized load, the integrated voltage harmonics factor (weighted THD) of the appropriate order is being minimized by applying one of the two mentioned modulation methods (SVC or QWS-SVPWM) for a current range of voltage amplitude modulation index. Like its components, the combined algorithm is suitable for MLVSI of any circuit configuration and any number of equal output voltage levels.

Space‐vector current control of cascaded half‐bridge three‐phase three‐wire voltage source inverter

Current controllers for voltage source inverters give better control of current waveform and also provide compensation for load transients and non-linearities. Despite the increasing employment of multilevel inverters in high-power medium voltage applications and its superior performance compared to two-level inverters, the extension of hysteresis current controllers to multilevel voltage source inverters is much less established. In this study, a current error space vector-based hysteresis controller is implemented on a three-phase cascaded half-bridge voltage source inverter. The vector-based method measures the current error in a space vector form and keeps the error within the assigned tolerance region. It has been observed from the simulation tests and experimental verifications that the implemented current regulator maintains the load current as close as possible to the set reference current with a significantly minimised error. Another attractive feature in the implemented closed-loop current controller is that the number of voltage levels is maintained as the output of the inverter with a fast dynamic response.

A study on performances of carrier-based pulse-width modulation techniques for three-phase three-level t-type neutral-point-clamped inverter under switch-open-circuit fault on two neutral-point-connected legs

Multilevel voltage source inverters (VSIs) have been used for several decades thanks to their advantages compared with traditional two level VSI. Among various types of multilevel configuration, the T-type neutral-point-clamped VSI (3L TNPC VSI or 333-type VSI) has gained the attention in recent years. Due to the unique structure, the 333-type VSI has critical issues in reliability in operation such as switch-open-circuit (SOC) and switch-short-circuit (SSC), which lead to several unrequired issues, for instance, reduction of system performance, distorted and unbalanced output voltages and currents, or triggering the protection circuits. In some applications, the amplitude reduction and harmonics distortion of output voltages in SOC faults are not acceptable. Therefore, it is necessary to develop a pulse-width modulation (PWM) algorithm for 333-type VSI working under SOC fault which guarantees the desired output fundamental component voltage. The simultaneous SOC fault on two neutral-point-connected legs in the 333-type VSI may cause a large reduction in the output voltage. Under this circumstance, the 333-type VSI becomes an asymmetrical one called 322-type VSI. Certain studies regarding to the operation of 333-type VSI under SOC faults have been carried out. However, these studies require more semiconductor devices in order to create a redundant switching circuit. This leads to higher system cost with reduced inverter effieciency due to the additional loss. In this study, two carrier-based pulse-width modulation (CBPWM) techniques, i.e. 322-sinusoidal PWM (322-SPWM) and 322-medium offset CBPWM (322-MOCBPWM) are proposed for 322-type VSI. The proposed techniques are firstly simulated in MATLAB/Simulink and then implemented on a hardware setup. Performances of the proposed techniques are evaluated in terms of total harmonic distortion (THD) and weighted-THD (WTHD) of output voltages. Simulation results show that considering the worst output voltage under SOC fault, vBC, the proposed 322-SPWM technique could improve the THD by 40% and the WTHD by 94% compared with the uncompensated case with m=0.8. The corresponding results of 322-MOCBPWM technique are 42% and 96%, respectively. Characteristics of THD and WTHD values are also presented for demonstration the effectiveness of the proposed algorithm.

Voltage Quality Enrichment using Transformerless Dynamic Voltage Compensator based on Asymmetrical Multilevel Inverter

In this article, Asymmetrical voltage source Multilevel Inverter based Transformerless Dynamic Voltage Compensator (ASMLI-TDVC) for load Voltage Quality (VQ) enrichment is proposed. The ASMLI-TDVC is controlled such that it compensates different levels of VQ problems with lesser Total Harmonic Distortion (THD). Synchronized voltage injection achieved through series transformer from traditional DVC leads to rise in the size of DVC and make system cumbersome. ASMLI based on less switch count topology is utilized for TDVC to overcome these aforementioned issues. Simulation studies of ASMLI-TDVC are carried out using Matlab Simulink software. Further, an experimental model is developed and tested in real-time using OP4500. Results prove that dynamic compensation for VQ improvement is achieved by ASMLI-TDVC.

A new multilevel inverter with reduced switch count for renewable power applications

This paper proposes a new technique for a voltage source multilevel inverter (MLI) with reduced switch count, and it creates a smoother sinusoidal output waveform with reduced total harmonic distortion (THD). Therefore, the proposed technique identifies a better position in the list of multilevel converters used for power quality conditioners. Semiconducting devices are added to it if the number of levels increases. In this work, the topology of MLI with reduced number of switches is presented. A new MLI is proposed with lower number of switches and sources in order to achieve higher level. The proposed topology is framed out with the combination of three half bridge and a single H-bridge configuration. Detailed simulation results for 15-level inverter of single and three phase inverters are presented in this paper. Three phase 15-level inverter is developed by employing three isolated different renewable sources and 21 switches.

Model-Free Predictive Current Control for Multilevel Voltage Source Inverters

This article proposes a generalization of the model-free predictive current controller (MFPCC) for multilevel voltage source inverters (VSIs). MFPCC is an alternative to mitigate the parameter sensitivity faced by model-based PCC (MPCC), but it requires a constant update of the stored current variations (CVs) associated with each VSI state to provide a prediction, which results in a satisfactory closed-loop response. When a multilevel VSI is considered the number of states increases, which results in a decrease of the CV update rate, since only one state can be updated at each sample. To solve this issue, the extended adjacent state scheme is used to reduce the possible number of solution candidates and then a controlled CV is used to compensate the updated CV. Simulation and experimental results obtained with a sampling rate of 5 kHz show that the proposed MFPCC exhibits performance similar to the one of MPCC for nominal parameters. However, a better current response is obtained in the case of the load parameter mismatch, especially at steady state.

Investigation of asymmetric concept on voltage source multilevel inverter for industrial applications

In a day to day life converter and inverters are ruled the world. This paper proposes the pulse width modulation technique implemented for multilevel inverter and it is produced a fifteen level single phase output. Total harmonics distortion have reduced, produced good quality of output and number of levels also increased. Proposed system having seven switches and three isolated battery source. The switching losses and switching stress also reduced. Multi carrier modulation Pulse width modulation technique implemented. The fifteen level of output voltages are 0, Vdc/7, −Vdc/7, 2Vdc/7, −2Vdc/7, 3Vdc/7, −3Vdc/7, 4Vdc/7, −4Vdc/7, 5Vdc/ 7, −5Vdc/7, 6Vdc/7, −6Vdc/7, V dc, −V dc from the input.

A Reduced Switch Five-Level VSI for High-Performance Vector Controlled PMSM Drive

This work presents the strategy for vector control of permanent magnet synchronous motor (PMSM) drive fed with a three-phase multi-level voltage source inverter for high performance. In the present work, the traditional 2-level inverter is replaced with a novel reduced switch 5-level inverter, and comparative analysis is done. The implementation of the five-level inverter improves the torque, stator current, and mechanical dynamics of the drive. Here PWM technique is employed to generate the gate pulses for switching devices in a planned sequence to obtain five-level output voltage. The 12 operating modes are defined for reduced switch 5-level inverter that produces voltages as 0, ±2Vdc/3, ±Vdc, ±4Vdc/3 with reduced total harmonics distortion (THD). The close-loop vector control of PMSM with developed five-level inverter is implemented to improve the performance of drive in terms of rise time, settling time, stator current harmonics. The overall system is developed in MATLAB/Simulink and investigations are done in different input command and loading conditions. An extensive simulation study and analysis of results reveal the potential of the present work. This work mainly focuses on the reduction of motor electromagnetic torque pulsations along with improved speed response.

Voltage Source Multilevel Inverters With Reduced Device Count: Topological Review and Novel Comparative Factors

Multilevel inverters (MLIs) have gained increasing interest for advanced energy-conversion systems due to their features of high-quality produced waveforms, modularity, transformerless operation, voltage, and current scalability, and fault-tolerant operation. However, these merits usually come with the cost of a high number of components. Over the past few years, proposing new MLIs with a lower component count has been one of the most active topics in power electronics. The first aim of this article is to update and summarize the recently developed multilevel topologies with a reduced component count, based on their advantages, disadvantages, construction, and specific applications. Within the framework, both single-phase and three-phase topologies with symmetrical and asymmetrical operations are taken into consideration via a detailed comparison in terms of the used component count and type. The second objective is to propose a comparative method with novel factors to take component ratings into account. The effectiveness of the proposed method is verified by a comparative study.

An efficient hybrid digital architecture for space vector PWM method for multilevel VSI

This paper presents an efficient, cost effective design implementation of a hybrid digital architecture for space vector pulse width modulation (SVPWM) method for multilevel inverters (MLIs). The SVPWM method is one of the most popular real time PWM method for three phase voltage source inverter (VSI). The implementation of SVPWM method becomes complex with an increase in the number of levels in a multilevel inverter. The SVPWM method for multilevel inverter is a multitask system. The main constraint when it comes to implementing SVPWM for multilevel inverters is the processing of dwell time computation and the generation of PWM gate signals for all of the switches with an accurate delay. A hybrid hardware structure consisting of a simple low-cost, low-power dsPIC micro controller (dsPIC 30F4011) and a state of the art Field Programmable Gate Array (FPGA) (Cyclone V 5CGXFC5C6F27C7N) is used to implement SVPWM. The proposed hybrid digital architecture utilizes the advantages and resources of the dsPIC and FPGA. The hybrid digital architecture meets the timing constraints of multitasking through synchronization and parallelism. A communication interface between the dsPIC and the FPGA reduces the design complexity. The software overhead for the communication interface remains fixed for any number of levels. The hybrid structure of the digital architecture provides scalability for the SVPWM method with more number of levels in multilevel inverter. The operation of the proposed hybrid digital architecture is experimentally validated with an optimized SVPWM method for a five level VSI. An optimized region identification algorithm and simple dwell time expressions are described for a five level SVPWM. The input DC of the five level VSI is obtained from a differential power processing (DPP) based PV system. Experimental results under different operating conditions are presented.

Circulating Current Suppression in Parallel Interleaved 2L VSIs Using Modified CM Offset Based Method During Inductors Mismatch Condition

Parallel interleaved two-level voltage source inverters (VSIs) could be analyzed as a single multilevel VSI and hence, a significance reduction in the grid side voltage and current ripple could be achieved. However, the parallel interleaved VSIs have a major issue of circulating current. The circulating current is mainly composed of two frequency components: high frequency component and low frequency component. The high frequency component is generated due to the instantaneous difference in the common-mode (CM) voltages of the VSIs. While due to inductance value mismatch in the ac side line frequency inductors, a low frequency circulating current also flows in the system. This low frequency component needs to be controlled as it could saturate the CM, coupled, or interphase inductors used for limiting the high frequency component of circulating current. In this article, an analysis is carried out for circulating current during the inductors mismatch condition. A CM offset signal is also proposed to limit the flow of low frequency component of the circulating current. The proposed CM offset is derived in terms of existing CM offset signals, and hence any existing pulsewidth modulation technique could be implemented using the proposed method. Simulation and experimental results show the improvement in the circulating current using the proposed modified offset.