Multilevel PWM Research Articles

Machine-learning based control of bi-modular multilevel PWM inverter for high power applications.

This paper presents the topology and machine learning-based intelligent control of high-power PV inverter for maximum power extraction and optimal energy utilization. Modular converters with reduced components economic and reliable for high power applications. The proposed integrated intelligent machine learning based control delivers power conversion control with maximum power extraction and supervisory control for optimal load demand control. The topology of the inverter, operating modes, power control and supervisory control aspects are presented. Simulation is carried out in MATLAB/SIMULINK to verify the feasibility of the proposed inverter and control algorithm. The experimental study is presented to validate the simulation results. The operational performance of the proposed topology is evaluated in terms of operational parameters such as regulation of output power, and load relay control and is compared to existing topologies. The economic performance is also evaluated in terms of power switch sizing and reliability in power delivery concerning switch or power sources failure.

Parallel-Connected Voltage Source Converters With a DC Common Mode and an AC Differential Mode PWM Filter

Two 3-phase converters can be connected in parallel using a range of inductor types. Coupled inductors used together with interleaved pulsewidth modulated (PWM) techniques can produce a high-quality multilevel PWM line output voltage. These inductors can be designed to have a high inductance between the two converter outputs to control circulating currents, combined with a low per-phase output inductance. Since the 3-phase PWM voltage between the two converters consists of two components, a differential mode and common mode, two inductor types can be used to separately filter the circulating currents produced by these two components. The inductor types presented places one coupled inductor between the 3-phase output terminals of the two converters, a <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3-limb CI</i> , and a second coupled inductor located between the two converter dc input terminals, a dc coupled inductor or <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dc choke</i> . The <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3-limb CI</i> filters circulating currents due to the differential mode PWM voltage and the <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dc choke</i> filters circulating currents due to the common mode PWM voltage. The <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dc choke</i> uses four windings in contrast to the six required of an equivalent common mode 3-phase ac choke. The two converters are operated with a filter capacitor across their dc input terminals. The 3-phase output of the two parallel converters is located at the center tap of the <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3-limb CI</i> windings in each phase and a very low effective per-phase output inductance is obtained. Consequently, the converter structure can supply very high-frequency fundamental output voltages with high-quality multilevel PWM line voltages. The performance of the coupled inductors presented is compared with a conventional coupled inductor and designs show that they can be 13% smaller with 16% lower losses. The parallel converter structure presented is suitable for high-power high-speed electric drives with applications in aerospace and electric vehicles where lightweight magnetics is required. Simulations and experimental results are presented for an 8 kW (300 Vdc, 208 Vac/22A) prototype operating with a fundamental frequency of 60 Hz –1.1 kHz.

Modified PDPWM control with MPPT algorithm for equal power sharing in cascaded multilevel inverter for standalone PV system under partial shading

&lt;span lang="EN-US"&gt;In this paper, a modified particle swarm optimization (MPSO) based maximum power point tracking (MPPT) controller is used to track the maximum power of a PV system using DC-DC boost converter technology. &lt;/span&gt;&lt;span lang="EN-GB"&gt;To raise the PV module's input DC voltage, a DC-DC boost converter was employed. The boost converter powered the DC-AC multilevel PWM inverter, which then delivered the output AC voltage to a solitary inductive load. Cascaded multilevel inverters are often used to condition power in renewable energy applications because they are easy to use and have few parts. Ripples in the voltage of DC link capacitors cause low order harmonics and inter harmonics in the multilevel inverter's output voltage. Phase disposition pulse width modulation (PDPWM) has the fewest harmonics. The inverter cells' power delivery is not equal in this manner. In the present paper, a strategy for improving sharing of power PDPWM for photovoltaic applications is proposed. The modified PDPWM is used on a 9-level inverter where each cell is connected to a PV array running at maximum power point tracking MPPT and under partial shadowing for single phase multilevel inverters. The MATLAB/SIMULINK software was used to do simulations, and the findings demonstrate that the method presented is effective at balancing the way power is shared between different inverter cells and reducing the voltage ripple of the DC link capacitor.&lt;/span&gt;

Minimization of total harmonic distortion in neutral point clamped multilevel inverter using grey wolf optimizer

&lt;span lang="EN-US"&gt;The inverter has been attracting researchers for their application in renewable energy. So far, multilevel inverter is considered as low distortion class, which produces multilevel output voltage imitating a pure sine waveform. However, the needs for free distortion of output voltage have been motivating to improve multilevel pulse width modulation PWM generation method. In this paper, the modified PWM technique is proposed to reduce the voltage total harmonics distortion (THD) of multilevel inverter. This modulation technique is then applied to control a single-phase threelevel neutral point clamped multilevel inverter (NPC-MLI). Grey wolf optimizer (GWO) algorithm is utilized to generate optimal amplitude and phase shift of modified reference signal. The GWO algorithm is then compared with other optimization algorithms such as differential evolution (DE), human psychology optimization (HPO), and particle swarm optimization (PSO) to evaluate their performance in harmonic minimization. The performance of the proposed work is validated through simulation and experimentation on a prototype. The results show that the modified PWM technique optimized with GWO can reduce THD on NPC-MLI output voltage.&lt;/span&gt;

Fully Automatized PWM Loss Calculation in Multiphase PMSM and Experimental Verification

A very simple and therefore wide-spread way to control motor speed and torque is to regulate the stator voltage by pulsewidth modulation (PWM). Depending on the modulation type, number of inverter levels, and modulation index of the PWM, various spectral components occur in the supply signal and inject ripple current in the motor phases. This current distortion can cause significant additional losses in the stator and rotor core, permanent magnets, and windings of an electric machine. Therefore, it is important to consider these losses in an early design stage. In this work, an efficient calculation method for harmonics of multilevel PWM signals and generated phase currents with different modulation types is presented. The PWM losses are calculated via 2-D finite element method analyses. The calculation and simulation workflow is realized within the software tool SyMSpace and applied to a three-phase permanent magnetic synchronous machine (PMSM). Loss measurements at different PWM frequencies and load points are conducted on a 3-phase PMSM. Since simulation and measurement results show good accordance, the proposed methods could be validated.

Analysis of power losses in multilevel pulse-width modulation inverters

The paper describes the types of multilevel pulse-width modulation, as well as methods for obtaining control signals for the inverter power switches for each of the types. The dependence of the harmonic composition of the output voltage of the inverter on the number of levels and the switching frequency of the keys of each level is analyzed. By modeling, the dependences of the transistor junction temperature on the number of voltage levels, switching frequency and load power are determined. The power switching system of an inverter with phase-shifted pulse-width modulation in high-frequency mode is analyzed, the dependence of switching losses on inductance is investigated. The ways of solving or improving the control systems of the conductivity losses of the converter flowing through the primary winding of a high-frequency transformer during the free-running period are formulated. The importance of this direction for the technological development of the economy, where efficiency improvements can lower individual utility bills, create jobs, and help stabilize electricity prices and volatility is shown. The most important stage of inverter design is called structural synthesis stage – the choice of topology and modulation algorithm that will ensure the greatest efficiency of the device. In addition, since the efficiency and reliability of inverters depend on the efficiency and reliability of secondary electricity consumers, the task of optimizing inverter circuits is a cornerstone for the effective development of technology and economy. The maximum dynamic power loss at a PWM frequency of 1 kHz reaches only 80 watts compared to the static power loss value of 800 watts

Non-line-of-sight WDM-MIMO optical camera communications with the DBPWR algorithm

Non-line-of-sight (NLOS) optical camera communications (OCC) is a potential wireless communication technology, which offers robustness to blocking and blooming effect, higher data throughput over longer transmission distances compared with line-of-sight OCC. In this work, we propose a wavelength division multiplexing (WDM)-multiple inputs multiple outputs (MIMO) NLOS OCC system with multi-level pulse width modulation (MPWM) and difference-based pulse width recognition (DBPWR) schemes. Signals on different color channels are separated through the RGB filter of the CMOS camera, while MPWM signals on the same color channel are separated using the DBPWR algorithm. Compared with the conventional threshold-based demodulation scheme, the proposed DBPWR scheme has lower complexity, higher reliability, and improved sampling frequency offset tolerance. A total data rate of 10.8 kb/s is experimentally demonstrated over more than 2 m NLOS link using the proposed WDM-MIMO OCC system, which is sufficient in many Internet of things applications.

Improved Modulation Strategy for Singe-Phase Cascaded H-Bridge Multilevel Inverter

In this letter, two new improved pulsewidth modulation (PWM) techniques are proposed for single-phase cascaded H-bridge inverter. Compared with the conventional modulation methods, including phase-shifted PWM (PS-PWM), level-shifted PWM (LS-PWM), discontinuous modulation (D-PWM), only PS-PWM can ensure the output quality and maintain the power balance between each module. That is why it is widely used. However, the switch with PS-PWM always operates in a high-frequency mode, resulting in the high switching losses and low efficiency. In order to solve the problem, two improved cascaded H-bridge multilevel PWM methods are proposed in this letter. With the proposed PWM methods, the power can be evenly distributed among modules, the utilization rate of switching devices is the same, while the switching times are reduced, which improves the system efficiency. Finally, the experimental tests are carried out on a digital-control single-phase cascaded H-bridge seven-level inverter. And the experimental results verify the effectiveness of the proposed solution.

Classification of Partial Discharges Originating From Multilevel PWM Using Machine Learning

A partial discharge (PD) is a small, localized breakdown which often appears in high-voltage insulation systems. PDs can be initiated within material defects such as voids or cracks when exposed to sufficiently high electric field levels. In this research work, we study and propose a machine learning (ML) approach to detect and classify PDs originating from multilevel pulsewidth modulation (PWM) waveforms as utilized in power electronic devices, such as inverters and variable frequency drives. Due to the increased use of power conversion units, new types of higher magnitude PDs have been observed to increase insulation degradation. By creating a cavity placed at different locations within the test object and exposing it to PWM voltage waveforms with two different rise times, a total of 345 660 PD events are recorded and organized into ten different classes. The maximum PD amplitude, duration, the time distance between consecutive PDs, and the area under the PD are used as features for PD classification. A unique way of concatenating a sequence of the extracted features to capture the temporal dependence of consecutive PDs is also presented. It is observed that when creating a sequence of information from consecutive observed PDs, a significant increase in classification accuracy can be obtained. Trained classifiers based on ensemble bagged decision trees (DTs) and long short-term memory (LSTM) architecture resulted in 95.3% and 98.5% average classification accuracy on test data respectively.

Comparison Study of Power Supplies in Real-Time Robust Control Systems of Vertical Plasma Position in Tokamak

The article is devoted to a comparative study of VIs (Voltage Inverters) in the RAO (Relay Auto-Oscillatory) mode and in the multilevel PWM (Pulse Width Modulation) mode as actuators in closed-loop control systems of vertical plasma motion in the T-15MD tokamak. The new digital multilevel PWM controller was developed. Both systems were put under equivalent conditions in terms of the same response to external signals. The discrete robust controller is single for both control systems and has been designed by LMI (Linear Matrix Inequalities) approach using the LPV (Linear Parameter Varying) plant model. The main criteria for comparison are the control power and signal spectrum on the HFC (Horizontal Field Coil). The simulations were performed on the real-time test bed consisting of two real-time target machines connected in a feedback loop “Plant Model – Controller”, to basically bring the system as close to reality as possible. The comparison results have showed the significant superiority of the 9-level PWM VI over the VI in RAO mode according to the selected criteria.

Minimum device usages of field programmable gate array (FPGA) verification of multilevel PWM inverter drive generation

Space Vector Pulse-Width Modulation (SVPWM) has now become an unavoidable PWM in the power electronics inverter development. If the SVPWM implementation can be made user-friendly, the operation can be easily soaked in by the future researchers and also the closed loop operation becomes sophisticated. This paper conveys a broad view about the state of art of different Field programmable gate array (FPGA) processors along with the inner views about the implementations of the 3-level SVPWM. The description of the different processors is discussed along with the implementation variance and also attempts to implement the SVPWM through Xilinx Spartan-III 3AN-XC3S400 using MATLAB-Xilinx System Generator (XSG) without deploying the direct Very High Speed Language (VHDL) code. It provides shortest translation designs into hardware implementations that are faithful, synthesizable and efficient, which permits the designer to minimise the time spent for the description and implementation of circuit. The synthesis result shows that the proposed implementation at 50 MHz frequency operation consumes a power of 13mW and occupies 1112 look up tables (LUTs) and 424 File File (FFs). Thereby, the Total Resource Utilization reduced drastically to 36%, which is far better than the other existing implementations. Also, the inference of less processing time can be seen from the synthesis.

Correction of errors and harmonic distortion in pulse-width modulation of digital signals

Pulse-Width (PW) modulation is widely used in those applications where an analog or digital signal has to be encoded in the time domain as a binary stream, such as switched-mode power amplifiers in transmitters of modern telecommunication standards, high-resolution digital signal conversion using single-bit digital-to-analog converters, and many others. Due to the fact that digital signals are sampled in the time domain, the quality of the resulting PW modulated waveforms is worsened by harmonic distortion. Multilevel PW modulation has been proposed to reduce these adverse effects, but the modulated waveform is no longer binary. In this paper, the mechanisms by which harmonic distortion is produced are analyzed. As a result, the distortion terms are mathematically quantified and used to correct the errors. Note that a correction network based on a simple subtraction of the distortion terms from the PW modulated signal would produce a waveform that would no longer be binary. The proposed correction network is implemented in the digital domain and, by means of a sigma-delta modulator, preserves the binary feature of the PW modulated output.

Hybrid Output Voltage Modulation (PWM-FSHE) for a Modular Battery System Based on a Cascaded H-Bridge Inverter for Electric Vehicles Reducing Drivetrain Losses and Current Ripple

This paper shows a preliminary study about the output voltage modulation of a modular battery system based on a seven-level cascaded H-bridge inverter used for vehicle propulsion. Two generally known modulation techniques, pulse width modulation (PWM) and fundamental selective harmonic elimination (FSHE), are extensively compared for such an innovative modular battery system inverter considering EVs’ broad torque-speed range. The inverter and the battery losses, as well as the inverter-induced current THD, are modeled and quantified using simulations. At low speeds, if the modulation index M is below 0.3, FSHE induces a high current THD (&gt;&gt;5%) and, thus, cannot be used. At medium speeds, FSHE reduces the drivetrain losses (including the battery losses), while operating at higher speeds, it even reduces the current THD. Thus, an individual boundary between multilevel PWM and FSHE can be determined using weightings for efficiency and current quality. Based on this, a simple hybrid modulation technique is suggested for modular battery system inverters, improving the simulated drive cycle efficiency by a maximum of 0.29% to 0.42% for a modeled small passenger vehicle. Furthermore, FSHE’s high speed dominance is demonstrated using a simple experimental setup with an inductive load.

Experimental validation of new self-voltage balanced 9L-ANPC inverter for photovoltaic applications

Multilevel inverters play an important role in extracting the power from renewable energy resources and delivering the output voltage with high quality to the load. This paper proposes a new single-stage switched capacitor nine-level inverter, which comprises an improved T-type inverter, auxiliary switch, and switched cell unit. The proposed topology effectively reduces the DC-link capacitor voltage and exhibits superior performance over recently switched-capacitor inverter topologies in terms of the number of power components and blocking voltage of the switches. A level-shifted multilevel pulse width modulation scheme with a modified triangular carrier wave is implemented to produce a high-quality stepped output voltage waveform with low switching frequency. The proposed nine-level inverter’s effectiveness, driven by the recommended modulation technique, is experimentally verified under varying load conditions. The power loss and efficiency for the proposed nine-level inverter are thoroughly discussed with different loads.

Non-conventional Cascade Multilevel Inverter with Lower Number of Switches by Using Multilevel PWM

The multilevel inverter is attracting the specialist in medium and high voltage applications, among its types, the cascade H bridge Multi-Level Inverter (MLI), commonly used for high power and high voltage applications. The main advantage of the conventional cascade (MLI) is generated a large number of output voltage levels but it demands a large number of components that produce complexity in the control circuit, and high cost. Along these lines, this paper presents a brief about the non-conventional cascade multilevel topologies that can produce a high number of output voltage levels with the least components. The non-conventional cascade (MLI) in this paper was built to reduce the number of switches, simplify the circuit configuration, uncomplicated control, and minimize the system cost. Besides, it reduces THD and increases efficiency. Two topologies of non-conventional cascade MLI three phase, the Nine level and Seventeen level are presented. The PWM technique is used to control the switches. The simulation results show a better performance for both topologies. THD, the power loss and the efficiency of the two topologies are calculated and drawn to the different values of the Modulation index (ma).

Analysis of Three Phase Nine Level Diode Clamped Multi Level Inverter

Compared to conventional inverter (square wave) multi-level inverter offers quality power owing to different voltage levels utilization in average and high voltage. Besides it also reduces Total Harmonic Distortion in the distributed system and dv/dt across power switches. This advantage is transcendently appropriate for cascaded diode connected converter that can be worked to create more number of levels using asymmetrical voltage source because of their integrated arrangement. However, this benefit no longer exist because it requires many dc links (batteries or rectifiers) which is costlier. Substitute method of implementing single low voltage floating DC link is to recompense voltage distortion using Neutral-Point-Clamped (NPC) converter. This NPC output and controlled floating single DC-link voltage along with controlled PWM strategy reduces the THD. This improves the bandwidth and make simpler the current control scheme. These motivated the study and analyze the performance of a Diode Clamp based three phase nine level multilevel inverterusingnovel PWM approaches in MATLAB 2014b and PROTEUS for hardware development. Thus low power prototype is developed and its performance is shown.

A High-Frequency Isolated Multilevel Cascaded-Type Bipolar Direct PWM AC–AC Converter for Utility Voltage Compensation

A high-frequency isolated multilevel cascaded-type bipolar direct PWM ac-ac converter is proposed. By cascading N-unit cells, the converter can produce symmetric bipolar voltage gain of ±ND. It does not require a separate ac source for each unit cell, and can provide higher ac output voltages with multiple levels using low-voltage rating devices, decreasing output voltage harmonics and filtering requirements. Moreover, phase-shift PWM switching is employed, increasing the effective frequency of the output filter, further reducing its requirements. The converter can be utilized as a dynamic voltage restorer (DVR) for grid voltage regulation, with the following features: No need for an external dc source, separate ac sources, and a line-frequency voltage injection transformer. Injection of higher voltage magnitudes than the line voltage, mitigating deep voltage sags. Injection of a negative series voltage to provide compensation for voltage swells. The detailed circuit operation is explained together with component design guidelines and application as DVR. Finally, experimental results are provided using an 800-W scale-down laboratory prototype.

A Class-D FVF LDO With Multi-Level PWM Gate Control, 280-ns Settling Time, and No Overshoot/Undershoot

A novel class-D flipped voltage follower (FVF) low-dropout (LDO) regulator is proposed and implemented in this paper to supply high load current with fast transient response for sharp load changes. The proposed class-D control generates a multi-level pulse width modulated (MLPWM) signal to the gate of the control transistor that corresponds to the load level. The MLPWM control signal enables wide loop bandwidth and reduces output ripple. The FVF architecture reduces the output impedance and improves the controller efficiency. A novel feed-forward transition-detection path (FFTDP) controls the gate of the power transistor and allows enhanced switching at high loads. The proposed LDO operates with a wide range of input voltages from 1.2V to 1.8V and dropout of 200mV down to 50mV. The implementation responds to load changes from 0-300mA in 7ns with no observed overshoot/undershoot. The output ripple for the LDO is $_{\mathbf {V}}=1$ mV with a current efficiency of 99.93% at maximum load current. The prototype chip is fabricated on 28-nm CMOS technology and the controller occupies 0.004mm2.

A linear programming approach for designing multilevel PWM waveforms

This paper considers the problem of designing a multilevel pulse width modulated (PWM) waveform with a prescribed harmonic content. Multilevel PWM design plays a major role in many diverse engineering disciplines. In power electronics, multilevel PWM design corresponds to determining the inverter switching times and levels for selective harmonic elimination and harmonic compensation. In mechatronics, the same design corresponds to shaping input signals to damp residual vibrations in flexible structures. More generally, in many applications, the aim of PWM design is to minimise the total harmonic distortion while adhering to a prescribed harmonic content. The solution approach presented in this paper is based on linear programming with the objective of minimising the total harmonic distortion. This objective is achieved within an arbitrarily small bound of the optimal solution of the related convex optimisation problem. In addition, the linear programming formulation makes the design of such switching waveforms computationally tractable and efficient. Simulations and experiments are provided for corroboration.

A Fast Multilevel SVPWM Method Based on the Imaginary Coordinate With Direct Control of Redundant Vectors or Zero Sequence Components

This paper for the first time comprehensively presents a multilevel space vector pulse width modulation (SVPWM) method based on the imaginary coordinate system. This method is probably one of the most efficient methods in fast multilevel SVPWMs. It avoids trigonometric operation, look-up tables and only requires simple logic judgement and arithmetic calculation. A distinct advantage of this method over other coordinate-transformation-based methods is that it does not need to transform from the imaginary coordinate system back to the a-b-c (or α-β) coordinate in order to select the redundant vectors using look-up tables. The redundant vectors or zero-sequence components are directly worked out in the proposed method, e.g., for balancing dc-link capacitor voltages, which avoids identifying the starting vector, vector rotation direction (clockwise or anti-clockwise), vector sequence, etc. as used in conventional methods. This paper entails each step to implement this SVPWM method, which can be replicated for multilevel converters with any number of voltage levels. The presented method has been used and validated by various converters, including a three-level and a five-level neutral-point-clamped converter. The archive value of this paper is that it demonstrates a milestone of fast multilevel SVPWM based on coordinate transformation.