Multilevel Inverter Structure Research Articles

Energy transformation without using filter on high resistive load

In this paper, 9-level, 17-level, 19-level, 21-level, 27-level, and 39- level inverters with SPWM are presented. According to a switching function, the high-multilevel inverter design has been described since a new multi-level inverter structure is considered. The multilevel inverter structure is designed with placing switches and sources on levels. Pulse width modulation, controlling switches in the inverter structure, is also produced by comparison between triangles and sinus signals. Operating sequences of the switches are given in the table in order to demonstrate the inverter operation characteristic with the produced signals. Then, mathematical equations are formed by considering an operation of switches on the load. In simulations and experiments, the 9-level, 17- level, 19-level, 21-level, 27-level, and 39-level inverters are performed on the resistance (R) and inductance (L) loads with different resistance, because it is difficult to generate current and voltage with an acceptable harmonic distortion on the impedances which have high ohmic values. After applications of experimentation and simulation, the obtained results are compared with other published papers of results and the international IEEE standard, which is 5% for harmonic distortions of creating currents and voltages.

Fuzzy based optimal switching angle-PWM controller for 27-level asymmetric multi-level inverter

This work aims to improve the operation of multi-level inverter with reduced switching losses, thereby propose a new structure for an MLI with a reduced component count. A 27-level asymmetric Multi Level Inverter (MLI) with a minimal number of static switches is considered as a test system. The proposed MLI is developed with three input DC sources and thirteen power electronic switches. The hardware prototype is developed for 40 V and 3.5 A output. The control logic is developed in dsPIC30F410 controller. The main objective of this work is to effectively bring down the Total Harmonic Distortion (THD) of the resulting output voltage by analyzing the harmonic spectrum of the proposed MLI configuration with various low frequencies switching techniques and optimizing their switching angles and to choose an appropriate switching state using fuzzy logic controller (FLC). The proposed FLC covers wide range of operating conditions i.e. 10 switching states and variables 9*9 rules to predict the suitable switching angel. The performance metrics of the proposed structure of 27-level MLI has been evaluated upon simulation results and experimental results based on hardware prototype. The comparative study also carried out with the recent MLI topologies.

Performance analysis of a modified reduce component count multilevel inverter

Reducing component in circuitry is desirable in many innovations. In multilevel inverter (MLI) perspective, the increasing of switching devices for a higher-level output will significantly increase power losses, thus affected the output harmonic distortion. In this paper, an extended and simplified three-phase reduce component count multilevel inverter (RCCMLI) structure adapted from S. S. Lee, Cascaded Compact-Module Multilevel Inverter (CCM-MLI) is demonstrated and analysed. Symmetrical reduce component structure with H-bridge inverter is considered in this work. For simplification purpose, the current path conduction for reverse current is not demonstrated in this paper. A simulation-based result is presented to observe the performance of RCCMLI with regards to its output voltage harmonic content. Related predetermined parameter values are included in this report. Particularly, this paper verified the aforementioned RCCMLI, but in higher level and three-phase application, which will further improve the pseudo-sinusoidal inverter output as it eliminates the triplens harmonic component compare to single-phase environment. As for the lower order odd harmonics elimination, computational algorithm namely Particle Swarm Optimization (PSO) has been implemented in the RCCMLI control strategy. In comparison to the traditional Cascaded H bridge (CHB), this work finds that employing the switching angle optimization in the proposed RCCMLI produce comparable improvement in minimizing the output voltage harmonic and able to bring the output quality closer to comply with IEEE 519 distortion limit with fewer components and compact size inverter.

Multiple switching pattern for a modified reduce switch multilevel inverter: A comparison analysis

A primary concern of multilevel inverter is its capability to produce desired alternating voltage close to sinusoidal at the output, using multiple sources of DC voltage input. Mostly a multilevel inverter is used to generate the AC voltage from DC voltage. The aim of this paper is to investigate the output of 9 level multilevel inverter by modifying the conventional 5 levels H-bridge cascade multilevel inverter. The proposed design intending to reduce the number of switches from 16 switches to 10 switches. Implementation of different switching pattern methods; equal phase (EP), half equal phase (HEP), half height (HH) and feed forward (FF) and the related expression are presented in this paper. In the result section shows a different percentage of total harmonic distortion achieved. Out of all 4 methods, HH method suppressed distortion wave the most and resulted in the lowest THD in the proposed inverter. This paper shows that by reducing the number of switches in multilevel inverter structure maintains the same quality output as the conventional H-bridge topology. Furthermore, the manipulation of the switches firing angle contribute in decreasing the system THD.

Closed-Loop Control and Performance Evaluation of Reduced Part Count Multilevel Inverter Interfacing Grid-Connected PV System

Multilevel inverters (MLIs) have drawn tremendous attention in the power sector. Application of MLI has grown extensively to improve the power quality and efficiency of the photovoltaic (PV) system. For an MLI interfacing PV system, the size, cost and voltage stress are the key constraints of the MLI that need to be minimized. This paper presents a novel reduced part count MLI interfacing single-stage grid-tied PV system along with a closed-loop control strategy. The proposed MLI consists of n repeating units and a level boosting circuit (LBC) that assists in generating 4n + 7 voltage levels instead of 2n + 3 levels. Three different algorithms are proposed for a proper selection of dc-link voltages to enhance the levels further. A comparative analysis is carried out to confirm the superiority of the developed MLI. The workability of the proposed MLI is investigated with a 1.3 kW PV system. The closed-loop control strategy ensures the maximum power tracking, dc-link voltage balancing, satisfactory operation of the MLI and injection of clean sinusoidal grid current under any dynamic changes. Comprehensive simulation analysis is carried out considering a 15-level MLI structure. Experimental tests further confirm the practicality of the topological advancement for a PV system under different dynamic conditions.

A New Configurable Topology for Multilevel Inverter With Reduced Switching Components

Multilevel inverters (MLI) are now becoming an important element for medium-voltage high-power applications. A low switch count MLIs are more popular due to their high efficiency, low cost, and easy control for the output having a higher number of levels. A new MLI topology for single-phase applications based on switched dc voltage source with reduced switch count is proposed in the paper. The presented topology is developed with the constraints of lesser blocking voltage of the switches with a higher number of levels at the output using a lower number of components. The proposed topology can also work in the symmetrical and asymmetrical configuration. Selective harmonic elimination (SHE) technique is applied to synthesize the staircase output voltages with eliminations of lower order harmonics by optimized computation of angles for switching operation. The comparative studies with the MLIs recommended in recent times show the importance of the proposed MLI structure in terms of reduced switch count and lower voltage stresses across switches in both asymmetrical and symmetrical configurations. The experimental results are presented to confirm the performance of the proposed topology.

Investigation of a Transistor Clamped T-Type Multilevel H-Bridge Inverter With Inverted Double Reference Single Carrier PWM Technique for Renewable Energy Applications

The Multilevel inverters (MLIs) are a new breed of power electronics converters. They are primarily used for the conversion of dc power to ac power. The two-level inverters are conventionally used to obtain ac power, but it requires operating the switches under very high switching frequency. Besides, the two-level inverter necessitates the use of LC filters with the switches operating under high dv/dt stress. The MLIs offer the advantage of utilizing several dc voltage sources to generate a stepped ac waveform with the proper arrangement of switches. Investigation of a Transistor Clamped T Type H-Bridge Multilevel Inverter (TC-TT-HB-MLI) with Inverted Double Reference Single Carrier PWM Technique (IDRSCPWM) for Renewable Energy Applications are discussed in this paper. A PV source is taken as an input to the TC-TT-HB-MLI. For different modulation indices like 0.85, 1 and 1.25, the FFT analysis is performed and presented, which corresponds to the variations in the irradiations from solar energy. A single unit of the TC-TT-HB-MLI is extended to a generalized MLI structure named Generalized Transistor Clamped T-Type H-Bridge Multilevel Inverter (GTC-TT-HB-MLI). The significant benefits of GTC-TT-HB-MLI are the multiple numbers of reductions in the switch count, and driver circuit counts for a higher number of MLI levels. Fast Fourier Transform (FFT) analysis is carried out on the MLI output to calculate the total harmonics distortion (THD). The experimental verification is performed using SPARTAN 3E-XCS250E; the gate signals are generated and provided to the switches.

Investigation of Multilevel Inverter for the Next Distributed Generation Using Low-Cost Microcontroller

Nowadays, more research projects have described a converter that is widely used at the distributed generation (DG) level in order to increase the amount of electrical power generation. The converter is known as an inverter when only one DG source is used or as a multi-inverter when several DGs are used. Here, the application of a multilevel inverter with a C2000 microcontroller (Texas Instruments (TI) TMS320F28335 microcontroller), which can be implemented with a current feedback loop, is investigated. This microcontroller acts as a communication interface between MATLAB SIMULINK and the multilevel inverter. Meanwhile, the current control model is modeled in MATLAB for designing the control strategy. It is where the multilevel inverter switches are triggered by using pulse-width modulation (PWM) signals generated by the microcontroller output. At the same time, the proportional integral derivative (PID) current control is used in order to allow the load current to follow the reference current. Based on the results, it can be summarized that the multilevel inverter is a very useful device for the next DG sources when it is combined with current control for load current distribution. From this investigation, it can be seen that in the future DGs could be connected to a multilevel inverter structure, where it will reduce the dependency on filter design and have a more sinusoidal output to the load for different DG power ratings.

Grid tied PV System using modular multilevel inverter

A grid tied photovoltaic system using modular multilevel inverter topology is proposed in this paper. Basic unit structure of modular multilevel inverter used in this system is capable of converting DC power from PV array to AC power for feeding power to the household loads or utility grid. The proposed modular multilevel inverter structure has lesser power electronic devices compared to the existing multilevel inverter topologies. The proposed system generates a nearly sinusoidal signal and achieves better output profile with low total harmonic distortion. Simulation of the proposed system is carried out in MATLAB/Simulink software and the results are presented.

Comparison Performance of Nine Level Multilevel Inverter Using Bipolar and Unipolar Switching Schemes

Multilevel inverter structures have the advantages due to the ablility to operate at high dc-bus voltage. It is able to operate at higher power applications by using series connection of switching devices. In addition, multilevel inverter can generate output voltage with very low harmonic distortion and synthesis a staircase voltage waveform by having multiple voltage levels. Various multilevel inverter topologies are introduced; however, cascaded multilevel inverter is commonly used because it is easy to be implemented. In addition, multilevel inverter topologies are able to operate at lower switching frequency and it produces higher efficiency by producing lower switching dissipation. In this paper, MATLAB/Simulink is used to model the seven levels cascaded multilevel PWM inverter by using bipolar and unipolar switching techniques. The analysis of the cascaded multilevel inverter will be done on different types of non-linear loads such as R-load, RL-load and RC-load The THD of voltages and currents on each type of loads that are done and finally the results are compared.

Power Quality Performance Evaluation of Multilevel Inverter With Reduced Switching Devices and Minimum Standing Voltage

Multilevel inverters (MLIs) have been extensively employed to improve the power quality of the photovoltaic (PV) systems. However, the need for large number of components, higher standing voltage, and high harmonic content in the output of a conventional MLI greatly affects the system efficiency. Asymmetrical MLIs have been therefore developed as a suitable alternative to address these issues. This article aims at developing such a hybrid asymmetrical structure suitable for PV application that has a high level per component ratio and minimum standing voltage. The proposed MLI is assembled using a reduced switch H-bridge-based (RSHB) MLI structure with n asymmetrical repeating units and different level doubling circuit (LDC) combinations. The two dc sources used in the repeating units are in the ratio of 1: n voltage ratio, and using n such units, the proposed MLI structures, i.e., PS1 and PS2 can synthesize 4 n + 5 and 4 n + 7 levels, respectively, at the output instead of 2 n + 3 levels with only RSHB MLI. Comparative analysis reveals that both PS1 and PS2 have fewer switches, low standing voltage, less power loss, and lower cost. A 3.9-kW standalone solar PV system is considered for performance evaluation of the PS1 structure applying both the selective harmonic elimination and carrier-based pulsewidth modulation control schemes. In light of this, dc-link voltage balancing and self-voltage balancing mechanism of the LDC are warranted. Extensive simulation of the proposed MLI is performed in MATLAB/Simulink platform under a change in modulation index, sudden load change, frequency change, and step change in solar insolation. Furthermore, theoretical and simulation findings are validated experimentally by performing similar tests on a prototype of the proposed 17-level MLI.

Single-Phase 13-Level Power Conditioning System for Peak Power Reduction of a High-Speed Railway Substation

: The control and operation of a single-phase 13-level power conditioning system (PCS) for peak power reduction of a high-speed railway substation (HSRS) are proposed. This PCS is a single-phase 3100 V, 2 MVA 13-level H-bridge multi-level inverter structure. It has excellent power quality. It is easy to serialize by voltage. In addition, the DC bus power of each cell inverter is supplied by lithium-ion batteries. The generalized reduction gradient optimization algorithm based on past load pattern is applied to the power management system for peak power reduction of HSRS. The phase detector and power controller for the control of a single-phase PCS based on virtually coordinated axes using an all-pass filter are expected to be robust to external disturbances with fast response characteristics. This study also proposes an adapted select switch (ASS) method that can change the switching depending on the operation state of PCS and the state of charge (SOC) of the battery to minimize battery imbalance by controlling each cell inverter of the H-bridge. The validity of the proposed system was confirmed by PSiM simulation and experiments using a demonstration system of 6 MW PCS and 2.68 MWh batteries at one of Gyeongbu high-speed line substations in Korea.

Investigation of modified multilevel inverter topology for PV system

Multilevel inverters become an alternative for high power and medium voltage applications in recent years. Multilevel inverters(MLI) are basically classified as Diode Clamped Multilevel inverter, Flying Capacitor Multilevel inverter, Cascaded H Bridge Multilevel Inverter (CHBMLI). The CHBMLI topology which consists of a series of H bridge unit with separate dc sources is mostly prefered to generate higher voltage levels, as it requires fewer components compared to the other topologies. As the level increases, the switching device requirement will be more and the circuit becomes large with this topology. To overcome this and to produce high quality output, reduced switch count topologies are the main focus in recent research.The reduced switch count structures are based on bidirectional switches, modified form of the structures, polarity and level generation based structure, reduced switch structures and hybrid topology structure. This paper proposes a three phase Modified Multilevel Inverter (MMLI) topology with reduced switch count for nine level and the topology is analyzed using different Pulse Width Modulation (PWM) technique. The proposed MLI structure consists of an H bridge unit with voltage conversion cell for each phase. It requires 24 switches for a 3Ф nine level inverter with eight switches per phase compared to 48 switches in CHBMLI. The Total Harmonic Distortion (THD) level of this topology is examined with the PWM techniques for symmetric and asymmetric DC voltage sources. THD results of the proposed MLI are compared with other reduced switch topology structure. The comparison result indicates that the proposed topology shows better harmonic level and reduced switches compared to that structure. A prototype of the proposed topology is built and is tested to validate with the simulation results. Simulation and experimental results show that the proposed topology produces a minimum harmonic level with fewer components.

Modified reduced device multilevel inverter structures with open circuit fault‐tolerance capabilities

Modified reduced device multilevel inverter structures with open circuit fault‐tolerance capabilities

GA Based Selective Harmonic Elimination for Multilevel Inverter with Reduced Number of Switches: An Experimental Study

In power electronic applications, especially high power and medium voltage, multilevel inverters (MLIs) have been commonly used. MLIs ensure high quality load voltage and lower Total Harmonic Distortion (THD) than traditional inverter. In this paper, a multilevel inverter structure with reduced number of power switches is proposed. The proposed multilevel inverter is lower costed than conventional MLI. Also, a Genetic Algorithm (GA) based Selective Harmonic Elimination (SHE) technique has been used for the first time in the proposed MLI structure with reduced number of switches. The proposed GA based SHE technique computes the optimum switching angles by solving nonlinear harmonic equations of multilevel inverter. Both Isochronous switching (IS) and SHE techniques have been applied to proposed MLI to demonstrate the effectiveness of the GA based SHE technique. Simulation and experimental results for 7, 11 and 13-level have been obtained. Results of 11-level inverter is analysed and given in detail. Results have clearly proved that desired order harmonics in proposed MLI topology can be eliminated by using GA based SHE technique and lower THD on the load voltage has been provided.

Cascaded H-bridge multilevel inverters with discrete variation of DC sources

ABSTRACTThis paper presents a new voltage regulation structure for multilevel inverters using discrete variation of DC sources. In the proposed method, discrete variation is achieved based on multi-tap transformers for applications where the DC sources are isolated and supplied by three-phase transformers, e.g., medium voltage (MV) motor drive applications. Moreover, by utilising the new solution, the number of required DC regulators is reduced significantly, for applications where the optimum modulation index with variable DC sources is used which suffer from large number of required converters. In addition, this paper proposes a new algorithm for optimising the switching angles, turn ratios of the multi-tap transformers and DC sources to maintain the voltage distortions at the standards levels for a wide range of output voltage regulation. To verify the feasibility of the new solution, a laboratory prototype is implemented based on a 2-cell cascaded H-bridge (CHB) multilevel inverter with unequal DC sources (with 9-level operation) while the proposed structure can be applied for other CHB multilevel inverters and switching strategies.

Normally Bypassed Cascaded Sources Multilevel Inverter with RGA Optimization for Reduced Output Distortion and Formulaic Passive Filter Design

The distributed generation involving multiple photovoltaic sources and synthesizing high-quality ac voltage from those multiple dc sources are nascent research ambits. A host of multilevel inverters (MLIs) has been ascertained for performing above errand diligently, where the component count is obnoxious. The single phase seven-level inverter is an acquiescent compromise between the circuit complexity and the quality of the output. Further enhancement on the performance can be succored through optimizing dc link voltages and switching angles. This paper proposes a component count pruned MLI structure and also a refined genetic algorithm (RGA)-based optimization scheme for the computation of both dc link voltages and switching angles. Previous attempts for this problem have solved the switching angles with the objective of resulting minimum harmonic content in the staircase-shaped output voltage. The dc link voltage of each level is however assumed to be the same and constant. As an extension, RGA-based optimization of both dc link voltages and switching angles is triumphed. The harmonic profile of the proposed switching strategy is simulated and also corroborated by a hardware prototype. In practice, the proposed fundamental switched strategy is apposite, in which each dc voltage can be self-maintained and independently controlled. In addition, a method for designing the passive LC filter is also presented.

A step‐up switched‐capacitor multilevel inverter based on 5‐level T‐type modules

The paper presents a new transformer-less step-up multilevel inverter structure with a single DC source. The concept was based on cascaded connection of bipolar T-type 5-level modules. Proper charging and discharging of capacitors across the load in prearranged time durations would make a nearly sinusoidal staircase voltage. The output voltage amplitude was several times greater than the DC input depending on the number of modules and charging mode of the capacitors. Multiplying the input voltage, self-balancing, generating bipolar voltage waveform, easy circuit expansion and considerably low THD (Total Harmonic Distortion) were found to be the advantages of the proposed topology. The paper also adds operating principle, simulation and experimental results of a 29-level prototype based on the presented inverter structure.

Reduced switch‐count structure for symmetric multilevel inverters with a novel switched‐DC‐source submodule

The aim of this study is to present a new cost effective topology for Symmetric multilevel inverters (SMLIs) configurations, which can generate a great number of output voltage levels with a least of switching devices. The proposed structure contains a novel switched-dc-source (SDCS) sub-module that can produce three positive output voltage levels with a contribution of four equal dc voltage sources, two unidirectional, and one bi-directional power switches. Accordingly, to create a uniform staircase output voltage with multiple levels, the proposed SDCS sub-module is integrated into a new design. Therefore, a new family of reduced switch-count (RSC)-SMLIs is derived, which is capable of generating at least 13- and 15-level output voltages using only ten power switches and nine gate drivers. Furthermore, when employing several of the proposed SDCS sub-modules in series, a new generalised RSC-SMLI topology is obtained. Comparisons with prior-art SMLIs structures are done, which also highlights the beneficial potential of the proposed topology. To demonstrate the superior performance of the proposed topology, several simulation and experimental results have been provided.

Switch Ladder Modified H-Bridge Multilevel Inverter With Novel Pulse Width Modulation Technique

It is difficult to make a structure of multilevel inverter for the efficient conversion of dc to ac having a smaller number of power electronic components, less switching losses, less voltage stress on switches, and a greater number of output voltage levels. To breakthrough this problem, a modification is performed in the existing H-bridge multilevel inverter to form a switch ladder modified H-bridge multilevel inverter (SLMHB-MLI). Moreover, for the minimization of maximum voltage rating on the switches and optimization of switching sequence of the multilevel inverter, a novel pulse width modulation (PWM) technique is proposed in this research. Furthermore, in SLMHB-MLI, the novel PWM technique is integrated with an ANDed PWM technique for the variation of output voltage magnitude. The usefulness of the proposed topology and PWM technique are confirmed via comparison with previous topologies simulation and experimentation, respectively.