Multilayer Electronic Packaging Research Articles

Tape casting system for ULTCCs to fabricate multilayer and multimaterial 3D electronic packages with embedded electrodes

A 3D multilayer structure built by two ultra-low temperature co-fired ceramic (ULTCC) compositions with silver embedded electrodes are co-fired at a temperature of 450°C. The 3D multilayer module is prepared by laminating the ULTCC green tapes with a new binder system, which organics can be completely burned out at temperature of 250°C before the sintering of the ULTCC 3D modulus. High-density microstructures are achieved for the sintered module. In this study, the ULTCC feasible binder system is introduced. Also, ULTCC multilayers and multimaterial structures with surface and embedded silver electrodes are fabricated. This research opens up a new horizon for fabrication of electroceramic devices with embedded electrodes in multimaterial devices.

The Effect of Processing Parameters on the Physical and Microwave Electrical Properties of Low Temperature Co-fired Ceramics

Low Temperature Co-fired Ceramics (LTCC) represent a multilayer electronic packaging technology with the ability to incorporate many electrical components such as conductive, resistive, and dielectric materials, into a single monolithic package. Example devices would include capacitors, inductors, resistors, antennae, transformers, hybrid circuits, etc. In general, the LTCC package consists of a glass/ceramic dielectric and compatible conductive inks (Au, Ag, etc.). The dielectrics and conductors are patterned/laminated to form the desired 3D structure and then co-fired to complete densification. The resulting monolithic block is mechanically robust with a high density of (often buried) electrical components. Typically, LTCC systems have found implementation in circuitry utilizing the RF and microwave frequency ranges. In general, the material design and processing parameters, and knowledge of how these affect the final mechanical and electrical properties of the LTCC package are needed for successful circuit design. The electronic performance of an LTCC dielectric/conductor system (Ferro L8) was investigated as a function of processing parameters (peak fire temperature, temperature ramp rate, furnace air flow, etc.). Comparisons were also made between multiple manufacturing sites as the mentioned processing parameters vary slightly from site to site even with nominally identical set points due to differences in furnace design, fab layout, etc. Material properties of fired parts such as effective permittivity and electrical losses were measured both on bare dielectric using resonant cavity methods and on the dielectric/conductor system as a whole using microstrip transmission line methods to frequencies as high as 50 GHz. Correlations were made between electrical performance and models based on material properties. The effects of varied processing parameters and processing sites were also studied and used to help establish process understanding and improvement with respect to high frequency electrical performance. As an example, optimization of electrical performance could be achieved by adjusting the nominal furnace temperature set point at a specific site where losses were slightly high even with identical processing parameters to those at another manufacturing site.

Dynamic Heat Transfer Inside Multilayered Packages with Arbitrary Heat Generations

In most engineering applications, e.g., hybrid electric vehicles, the multilayered electronic packages generate arbitrary heat over a transient thermal duty cycle. In addition, the outer surface of such media endures time-dependent temperature as a result of variable coolant temperature during driving/duty cycles. As such, a new analytical model is developed to predict transient heat conduction inside multilayered composite media with arbitrary heat generation inside the layers. It is assumed that the temperature of the outer surface varies periodically over time. New compact closed-form relationships are developed for calculating 1) the temperature distribution inside multilayered media, 2) the average temperature of each layer, and 3) the interfacial heat flux. As an example, the methodology is applied to a two-concentric-cylinder composite. A detailed parametric study is conducted, and the critical values for the dimensionless parameters are evaluated; beyond these values, the temperature field inside the media is not affected considerably for any combination of other variables. It is shown that there is an optimum angular frequency that maximizes the amplitude of the interfacial heat flux. An independent numerical simulation is also performed using commercially available software ANSYS; the maximum relative difference between the obtained numerical data and the analytical model is less than 2%.

Radiation Mechanisms and Electromagnetic Interference in Ceramic Electronic Packages

A full-wave electromagnetic analysis for characterizing typical electromagnetic shielding practices in ceramic electronic packages is presented. Typically in printed circuit board emissions, the power plane emissions, and exposed surface nets are considered, however, the signal interconnect from the PCB to an electronic package can also be a significant source of radiation and hence an electromagnetic interference (EMI) issue. In this paper we describe electromagnetic radiation mechanisms resulting from high-frequency and high-speed applications in ceramic multilayer electronic packages and review the typical practice of implementing via fences to mitigate and reduce the EMI risk within a package substrate and also for the case when the package is part of a package/board configuration.

Cascaded Microwave Network Approach for Power and Signal Integrity Analysis of Multilayer Electronic Packages

In this paper, an efficient cascaded microwave network approach is presented for power and signal integrity analysis of multilayer printed-circuit boards (PCBs) and advanced electronic packages with multiple signal traces, multiple power-ground plates, multiple vias, and external loads such as decoupling capacitors. Each parallel-plate pair, which consists of two consecutive conductor plates functioning as either power or ground in the PCBs or packages, is modeled as one individual microwave network. Equivalent circuits are used in the microwave network to model the vias, and a parallel-plate impedance matrix is formulated to account for the wave interactions between the vias and the boundary of the PCB or package. If signal traces are present in a plate pair, a modal decomposition and recombination approach is employed to model two associated modes: the transmission line mode for the signal traces, and the parallel-plate mode for the power-ground plate pair. The microwave networks for each plate pair are finally cascaded together by enforcing the continuity of the voltages and currents at the via clearance holes in the conductor plate shared by two consecutive plate pairs. Numerical validation reveals that the cascaded microwave network approach produces accurate simulation results with much less central processing unit time and memory requirements than 3-D full-wave approaches.

Effect of current density on the pulsed co-electrodeposition of nanocrystalline nickel-copper alloys

Nanocrystalline coatings have become an essential component of single and multilayer electronic packaging, ship building, mining, magnetorestrictive applications, etc. In the current work, nanocrystalline Ni-Cu films were synthesized by pulsed electrode-position using a citrate bath. Cathodic polarization experiments were carried out for optimization of bath composition to co-deposit nanocrystalline Ni-Cu films. Depositions were optimized between the current density range of 0.05–0.25 A·cm−2 to achieve a uniform equiaxed coating with a target Ni content of greater than 70% owing to their superior corrosion resistance and enhanced hardness.

A Semi-Analytical Approach for System-Level Electrical Modeling of Electronic Packages With Large Number of Vias

This paper presents a semi-analytical approach for electrical performance modeling of complex electronic packages with multiple power/ground planes and large number of vias. The method is based on the modal expansion technique and the method of moments. For the inner package domain with multiple power/ground planes and many vias, the modal expansion method is employed to compute the electromagnetic fields from which the multiport network parameters, e.g., the admittance matrix can be easily obtained. For the top/bottom domain of signal layers, the moment method is used to extract the equivalent resistance, inductance, capacitance, and conductance (RLCG) parameters. The equivalent circuit for the entire package is then generated by combining the results for both package domains. The equivalent circuit can be used in a SPICE-like simulator to study the signal and power integrity of an electronic package. Numerical examples demonstrate that the new approach is able to provide fast yet accurate signal and power integrity analysis of multilayered electronic packages.

Molecular Dynamics Simulation of Thermal Cycling Test in Electronic Packaging

Interfacial failure under thermal cycling conditions is one of the main concerns in package design. To minimize such failure in multi-layered electronic assemblies and packages, it is important to develop a better understanding of the reliability at a molecular level. In this paper, molecular dynamics (MD) simulations were conducted to investigate the interfacial energy of the epoxy molding compound (EMC) cuprous oxide system during the thermal cycling test. In order to investigate the effect of the cuprous oxide content in the copper substrate on the interfacial adhesion, two kinds of MD models were examined in this study. The results revealed that the cuprous oxide content in the copper substrate had a large effect on the interfacial adhesion between the EMC and copper, which is consistent with the experimental observation.

Thermoelastic solutions for multilayered electronic assemblies

The presence of dissimilar material systems and thermal gradients introduces thermal stresses in multilayered electronic assemblies and packages during fabrication and operation. The thermal stresses of multilayered electronic assemblies near free edges play an important role in determining their reliability. Therefore, it is important to provide designers a good estimate of stresses near free edges. According to the heat conduction mechanism of integrated circuits, the temperature field in the chip, adhesive layer and substrate is derived and solved when the chip works in a steady state. Taking the temperature field in the chip, adhesive layer and substrate as the heat source, we solve the thermal stress field in the chip, adhesive layer and substrate by using the technique of Fourier's series expansion. The effects of the geometric parameters of the chip, adhesive layer and substrate on thermal stresses are analyzed. From the analysis of thermal stresses in the chip–adhesive layer–substrate structure, it can be found that the stress concentration near free edges is more prominent. In the design of electronic packagings, the stress concentration near free edges which may lead to the failure or malfunction of electronic assemblies and packages should be taken into account in detail.

Investigation of moisture diffusion in electronic packages by molecular dynamics simulation

Moisture-related failure is one of the main concerns in the integrated circuit (IC) package design. To minimize such failure in multi-layered electronic assemblies and packages, it is important to develop a better understanding of the reliability at a molecular level. In this paper, molecular dynamics (MD) simulations were conducted to investigate the respective moisture diffusion into the epoxy molding compound (EMC) and at the EMC/Cu interface. Moisture diffusion coefficients into the bulk EMC material and at the EMC/Cu interface can be derived from the mean-squared displacements calculated from MD simulations. The MD results showed that the seepage along the EMC/Cu interface is more prevalent when compared to moisture diffusion into the bulk EMC and, thus, rendering it a dominant mechanism causing moisture induced interfacial delamination in plastic packages.

The Thermoelastic Analysis of Chip-Substrate System

The presence of dissimilar material systems and thermal gradients introduces thermal stresses in multi-layered electronic assemblies and packages during fabrication and operation. The thermal stresses of the chip-substrate structure near free edges play an important role in determining the reliability of electronic packaging structures. Therefore, it is important to provide designers a good estimate of free edge stresses. According to the heat conduction mechanism of integrated circuits, the temperature field distribution in the chip and substrate is derived and solved when the chip works in a steady state. Taking the temperature field in the chip and substrate as the heat source, we solve the thermal stress field in the chip and substrate by using the technique of Fourier’s series expansion. The effects of geometric parameters of the chip and substrate on thermal stresses are analyzed. From the analysis of thermal stresses in the chip-substrate structure, it can be found that the stress concentration near free edges is more prominent. In the design of electronic packagings, the stress concentration near free edges which may cause cracking and delamination leading to the failure or malfunction of electronic assemblies and packages should be taken into account in details.

Warpage Analysis of Underfilled Wafers

Wafer-level packaging (WLP) is one of the future trends in electronic packaging. Since 1994, many companies have released various WLP licenses. One of the common concerns of WLP is wafer warpage. Warpage of wafers tends to introduce cracking or delamination during dicing and low temperature storage processes. After wafer dicing, warpage could affect the quality of the dies and shorten the life of each packaged product. Many documented works indicated that in the design and implementation of multilayer structured electronic packaging products, some key parameters must be carefully considered and closely controlled to ensure the best packaging quality with the minimum warpage. During the wafer-level flip chip assembly process, the application of underfill on the whole wafer is a critical step. In this step, the key underfill parameters that affect wafer warpage are Young’s modulus, thickness, and coefficient of thermal expansion (CTE). In this paper, an experimental design and statistical methods were used to identify the model structure and parameters that are critical to the warpage of wafers. Bilinear regression models were identified based on the data obtained from finite element analysis (FEA) that was verified by shadow moire´ experiments. In FEA, the underfilled wafer structure is simplified to consisting of two layers of linear elastic materials. According to the models, the CTE, the coupling of Young’s modulus and CTE, and the coupling of thickness and CTE primarily determine wafer warpage. Further FEA and shadow moire´ experiments indicate that the models are capable of predicting wafer warpage in the WLP processes.

Interfacial Thermal Stress Analysis of Anisotropic Multi-Layered Electronic Packaging Structures

The presence of dissimilar material systems and thermal gradients introduce thermal stresses in multi-layered electronic assemblies and packages during fabrication and operation. The high stress gradients near the free edge of bonding interfaces of such structures may cause cracking and delamination leading to the failure or malfunction of electronic assemblies and packages. A simple but accurate engineering approach for the calculation of interlaminar thermal stresses due to thermal mismatch in multi-layered structures is needed so that designers can determine interlaminar thermal stresses easily without much computational efforts. A few approaches based on the generalized deformation theory have been published but most of them are only suitable for structures with symmetric layers. For electronic packages and assemblies, unsymmetric layers are often used. An improved approach, Classical Laminate Theory-Edge Stress Shape (CLT-ESS), for prediction of interlaminar thermal stresses that can be applied to multi-layered structures with unsymmetric layers is presented. Comparisons are made with finite element analysis results and are found to be favorable. The proposed approach provides an efficient way for the calculation of interlaminar thermal stresses. [S1043-7398(00)00901-4]

Electron beam machining of ceramic green-sheets for multilayer ceramic electronic packaging applications

High power electron beams can be used to machine vias and interconnecting structures in ceramic green-sheets. The advantages of this technology are: direct maskless metallization, noncontact machining of high density via and interconnecting structures of fine dimensions. These features translate themselves into design and development of state of the art multilayer ceramic (MLC) packaging on a quick turn around basis from design to build. Electron beam technology offers accurate machining of three dimensional interconnecting line structures. Vias of aspect ratio > 3 and diameters as small as 30 μm have been fabricated.

Metal-ceramic constraints for multilayer electronic packages

Ceramic formulations set in an organic binder are currently being cast in thin paper-like sheets. These sheets may be punched, screened with metal pastes, and laminated to form a composite of metal and ceramic particles held together by an organic medium. By slowly burning off the organic binder and then sintering the ceramic and metal together, a substrate with many layers of interconnecting wiring may be obtained. The coincident sintering of the ceramic and metal phases presents compatibility constraints. Temperature considerations with respect to shrinkage and coefficient of expansion match between the ceramic and metal phases as well as solid/solid and solid/ambient interactions are important constraints in the fabrication of these composites. High conductivity metals (e.g., Ag, Cu) are generally not available for co-firing because sintering temperatures of important ceramic formulations are higher than the melting points of these metals. This constraint has been minimized through the use of capillary infiltration of molten metals into the ceramic structure. Consequently, it is now possible for multilayer ceramic structures to provide the interconnection wiring densities and conductivities necessary to respond to the needs of greater circuit densities of integrated circuit chips. Material selections are reviewed on the basis of electrical properties, ambient interactions, stresses due to sintering shrinkage, and thermal coefficient of expansion. Certain problems, tradeoffs, and procedures used in the fabrication of a multilayer substrate with Cu-filtrated lines are discussed.