Thermoelastic solutions for multilayered electronic assemblies

Abstract

The presence of dissimilar material systems and thermal gradients introduces thermal stresses in multilayered electronic assemblies and packages during fabrication and operation. The thermal stresses of multilayered electronic assemblies near free edges play an important role in determining their reliability. Therefore, it is important to provide designers a good estimate of stresses near free edges. According to the heat conduction mechanism of integrated circuits, the temperature field in the chip, adhesive layer and substrate is derived and solved when the chip works in a steady state. Taking the temperature field in the chip, adhesive layer and substrate as the heat source, we solve the thermal stress field in the chip, adhesive layer and substrate by using the technique of Fourier's series expansion. The effects of the geometric parameters of the chip, adhesive layer and substrate on thermal stresses are analyzed. From the analysis of thermal stresses in the chip–adhesive layer–substrate structure, it can be found that the stress concentration near free edges is more prominent. In the design of electronic packagings, the stress concentration near free edges which may lead to the failure or malfunction of electronic assemblies and packages should be taken into account in detail.