Multidimensional Loop Research Articles

Loop interchange and tiling for multi-dimensional loops to minimize write operations on NVMs

Non-volatile memory (NVM) is expected to be the second tier of memory in two-tier memory systems. However, because of the limited write endurance, it is vital to reduce the number of writes on NVM. Large-scale nested loops are the performance bottleneck in programs since the data cannot be held on the first tier of memory and then causes many write operations on NVM. Loop tiling groups iterations and loop interchange changes the execution order of the loop to improve data locality and thus reduce communication with NVM. However, research that combines loop interchange and loop tiling for minimizing writes on NVM is uncommon. In this paper, we propose a new loop tiling scheme and combine the loop interchange to solve these issues. Specifically, we propose a strategy to generate the legal tile shape, which is a parallelogram, first. Then, we propose an optimal tile size selection technique to minimize the write operations on NVM. In addition, we adopt the loop interchange technique to help loop tiling generate an optimal tile size for multi-dimensional loops. Finally, we schedule the accessing operations and computations in a pipeline fashion to cover the NVM latency. Experiments show that the proposed scheme can reduce the write on NVM efficiently. In addition, for 2-dimensional loops, NVM latency can be completely hidden.

A Multivariate Analysis Framework for Vehicle Detection From Loop Data Under Heterogeneous and Less Lane Disciplined Traffic

Accurate vehicle detection in real-time is a challenging problem for engineers and researchers working in the field of transportation engineering all over the world. To detect the vehicle presence in the lane-based traffic, one of the widely used traffic detectors is inductive loop detectors (ILD). For less lane disciplined and heterogeneous traffic, researchers have suggested another traffic detector known as a multiple inductive loop detector (MILD) system. In order to extract the vehicle count from MILD data, it is required to detect vehicle presence and segment the signature of different vehicles. This work is focused on the automated processing of MILD signals to get total vehicle count information in real-time under heterogeneous and less-lane disciplined traffic conditions. This study proposes a multivariate data analysis framework for the detection and segmentation of vehicle signature from the acquired data, without significant manual intervention. The major challenge in this process is the coupling of the multi-dimensional loop data, due to cross-talk across the loops. To address this, principal component analysis (PCA) is used with the additional benefit of dimensionality reduction. Though PCA is a well-known method, its application to the current problem is not trivial and calls for the tailoring of the method. Here, a new PC selection strategy suitable for data under consideration is proposed, as the traditional approach does not fit this application and tends to be low accuracy. Subsequently, the principal components are processed using a threshold-based method, which uses the mean absolute deviation measure, to detect the vehicle presence. The results show that the developed algorithm with the proposed strategy for PC selection achieved an average vehicle count accuracy of 90.38 % whereas with the traditional approach the accuracy is 24.31 %.

Multi-loop magnetisation method for detecting coal mine wire rope defects

Existing methods for detecting magnetic leakage signals from damaged wire ropes require axial saturation magnetisation and the accuracy of the detection equipment depends on the degree of saturation of the magnetisation. Moreover, owing to the special characteristics of the structure, diameter and operating environment of the wire rope, it is difficult to achieve the expected magnetisation effect. Consequently, in addition to other issues, the detection accuracy and versatility of the equipment are low. This study proposes a method based on spatial multi-dimensional orthogonal array loop magnetisation to detect coal mine wire rope defects. First, a sensor excitation structure model is developed. Then, a method for detecting the radial magnetic flux using permanent magnet arrays is analysed and the influence of the number of permanent magnet radial magnetic blocks on the magnetisation effect is studied. In addition, a wire rope detection method based on the principle of clustering is investigated and used to discuss the influence of the shape, structure and size of the sensor on the magnetisation effect. Finally, through laboratory experiments, the applicability of the test model and the proposed method are verified. The results show that the magnetisation effect is better and more cost-effective when the number of permanent magnet radial magnetic blocks is eight and that the proposed detection method can effectively identify damaged wire rope joints. Furthermore, the proposed equipment achieves a signal-tonoise ratio of 28 dB, thereby improving the reliability of damage detection.

Tiled parallel 2D computational processes

The algorithm implemented on a parallel computer with distributed memory has, as a rule, a tiled structure: a set of operations is divided into subsets, called tiles. One of the modern approaches to obtaining tiled versions of algorithms is a tiling transformation based on information sections of the iteration space, resulting in macro-operations (tiles). The operations of one tile are performed atomically, as one unit of calculation, and the data exchange is done by arrays. The method of construction of tiled computational processes logically organized as a two-dimensional structure for algorithms given by multidimensional loops is stated. Compared to one-dimensional structures, the use of two-dimensional structures is possible in a smaller number of cases, but it can have advantages when implementing algorithms on parallel computers with distributed memory. Among the possible advantages are the reduction of the volume of communication operations, the reduction of acceleration and deceleration of computations, potentially a greater number of computation processes and the organization of data exchange operations only within the rows or columns of processes. The results are a generalization of some aspects of the method of construction of parallel computational processes organized in a one-dimensional structure to the case of a two-dimensional structure. It is shown that under certain restrictions on the structure and length of loops, it is sufficient to perform tiling on three coordinates of a multidimensional iteration space. In the earlier theoretical studies, the parallelism of tiled computations was guaranteed in the presence of information sections in all coordinates of the iteration space, and for a simpler case of a one-dimensional structure, in two coordinates.

Partition Scheduling on Heterogeneous Multicore Processors for Multi-dimensional Loops Applications

This paper addresses the scheduling problem for multi-dimensional loops applications on heterogeneous multicore processors. In the multi-dimensional loops scheduling problem, a significant issue is how to hide memory latency to reduce the schedule length. With the increasing CPU speed, the gap between the processor and memory performance is an important bottleneck for modern high-performance computer systems. To solve the bottleneck problem, a variety of techniques have been studied to hide memory latency from intermediate fast memories (caches) to various prefetching and memory management techniques. Although there are a lot of algorithms in the literature to solve the scheduling with memory management problem for multiprocessor systems, they may not deliver good quality with high performance for heterogeneous multicore processors. In this paper, we first propose a scheduling algorithm Recom_Task_Assign to reduce the write activities to main memory. Then, in conjunction with the Recom_Task_Assign algorithm, we present a new partition scheduling algorithm called heterogeneous multiprocessor partition (HMP) based on the prefetching technique for heterogeneous multicore processors, which can hide memory latencies for applications with multi-dimensional loops. This technique takes advantage of memory access pattern information and fully considers the heterogeneity of processors to achieve high processor utilization. Our HMP algorithm selects the appropriate partition size and shape according to different processors, which increases processor utilization and reduces memory latency. Experiments on DSP benchmarks show that our algorithm can efficiently reduce memory latency and enhance parallelism compared with existing methods.

Practical Multidimensional Branch Prediction

The most efficient branch predictors proposed in academic literature exploit both global branch history and local history. However, local history predictors introduce major design challenges, particularly for the management of speculative histories. The wormhole (WH) branch predictor was recently introduced to exploit branch outcome correlation via multidimensional histories. For some branches encapsulated in a multidimensional loop, their outcomes are correlated with those of the same branch in neighbor iterations, but in the previous outer loop iteration. Unfortunately, the practical implementation of the WH predictor is even more challenging than the implementation of local history predictors. This article introduces a practical, cost-effective mechanism for capturing multidimensional branch correlations: the innermost-loop iteration (IMLI) counter.

Sensitivity Analysis of Deviation Source for Fast Assembly Precision Optimization

Assembly precision optimization of complex product has a huge benefit in improving the quality of our products. Due to the impact of a variety of deviation source coupling phenomena, the goal of assembly precision optimization is difficult to be confirmed accurately. In order to achieve optimization of assembly precision accurately and rapidly, sensitivity analysis of deviation source is proposed. First, deviation source sensitivity is defined as the ratio of assembly dimension variation and deviation source dimension variation. Second, according to assembly constraint relations, assembly sequences and locating, deviation transmission paths are established by locating the joints between the adjacent parts, and establishing each part’s datum reference frame. Third, assembly multidimensional vector loops are created using deviation transmission paths, and the corresponding scalar equations of each dimension are established. Then, assembly deviation source sensitivity is calculated by using a first-order Taylor expansion and matrix transformation method. Finally, taking assembly precision optimization of wing flap rocker as an example, the effectiveness and efficiency of the deviation source sensitivity analysis method are verified.

Combining multidimensional loops and its application

A method of uniting of multidimensional loops and its application for low power embedded systems and high-performance computing

Iterational retiming with partitioning

The widening gap between processor and memory performance is the main bottleneck for modern computer systems to achieve high processor utilization. To hide memory latency, a variety of techniques have been proposed—from intermediate fast memories (caches) to various prefetching and memory management techniques. In this article, we propose a new loop scheduling with memory management technique, Iterational Retiming with Partitioning (IRP), that can completely hide memory latencies for applications with multidimensional loops on architectures like CELL processor. In IRP, the iteration space is first partitioned carefully. Then a two-part schedule, consisting of processor and memory parts, is produced such that the execution time of the memory part never exceeds the execution time of the processor part. These two parts are executed simultaneously and complete memory latency hiding is reached. In this article, we prove that such optimal two-part schedule can always be achieved given the right partition size and shape. Experiments on DSP benchmarks show that IRP consistently produces optimal solutions as well as significant improvement over previous techniques.

Register allocation for software pipelined multidimensional loops

This article investigates register allocation for software pipelined multidimensional loops where the execution of successive iterations from an n -dimensional loop is overlapped. For single loop software pipelining, the lifetimes of a loop variable in successive iterations of the loop form a repetitive pattern. An effective register allocation method is to represent the pattern as a vector of lifetimes (or a vector lifetime using Rau's terminology [Rau 1992]) and map it to rotating registers. Unfortunately, the software pipelined schedule of a multidimensional loop is considerably more complex and so are the vector lifetimes in it. In this article, we develop a way to normalize and represent the vector lifetimes, which captures their complexity, while exposing their regularity that enables a simple solution. The problem is formulated as bin-packing of the multidimensional vector lifetimes on the surface of a space-time cylinder. A metric, called distance, is calculated either conservatively or aggressively to guide the bin-packing process, so that there is no overlapping between any two vector lifetimes, and the register requirement is minimized. This approach subsumes the classical register allocation for software pipelined single loops as a special case. The method has been implemented in the ORC compiler and produced code for the IA-64 architecture. Experimental results show the effectiveness. Several strategies for register allocation are compared and analyzed.

Single-dimension software pipelining for multidimensional loops

Traditionally, software pipelining is applied either to the innermost loop of a given loop nest or from the innermost loop to outer loops. This paper proposes a three-step approach, called single-dimension software pipelining (SSP) , to software pipeline a loop nest at an arbitrary loop level that has a rectangular iteration space and contains no sibling inner loops in it. The first step identifies the most profitable loop level for software pipelining in terms of initiation rate, data reuse potential, or any other optimization criteria. The second step simplifies the multidimensional data-dependence graph (DDG) of the selected loop level into a one-dimensional DDG and constructs a one-dimensional (1D) schedule. Based on the one-dimensional schedule, the third step derives a simple mapping function that specifies the schedule time for the operation instances in the multidimensional loop. The classical modulo scheduling is subsumed by SSP as a special case. SSP is also closely related to hyperplane scheduling, and, in fact, extends it to be resource constrained. We prove that SSP schedules are correct and at least as efficient as those schedules generated by traditional modulo scheduling methods. We extend SSP to schedule imperfect loop nests, which are most common at the instruction level. Multiple initiation intervals are naturally allowed to improve execution efficiency. Feasibility and correctness of our approach are verified by a prototype implementation in the ORC compiler for the IA-64 architecture, tested with loop nests from Livermore and SPEC2000 floating-point benchmarks. Preliminary experimental results reveal that, compared to modulo scheduling, software pipelining at an appropriate loop level results in significant performance improvement. Software pipelining is beneficial even with prior loop transformations.

Register allocation for software pipelined multi-dimensional loops

Software pipelining of a multi-dimensional loop is an important optimization that overlaps the execution of successive outermost loop iterations to explore instruction-level parallelism from the entire n-dimensional iteration space. This paper investigates register allocation for software pipelined multi-dimensional loops.For single loop software pipelining, the lifetime instances of a loop variant in successive iterations of the loop form a repetitive pattern. An effective register allocation method is to represent the pattern as a vector of lifetimes (or a vector lifetime using Rau's terminology) and map it to rotating registers. Unfortunately, the software pipelined schedule of a multi-dimensional loop is considerably more complex, and so are the vector lifetimes in it.In this paper, we develop a way to normalize and represent vector lifetimes in multi-dimensional loop software pipelining, which capture their complexity, while exposing their regularity that enables us to develop a simple, yet powerful solution. Our algorithm is based on the development of a metric, called distance , that quantitatively determines the degree of potential overlapping (conflicts) between two vector lifetimes. We show how to calculate and use the distance, conservatively or aggressively, to guide the register allocation of the vector lifetimes under a bin-packing algorithm framework. The classical register allocation for software pipelined single loops is subsumed by our method as a special case.The method has been implemented in the ORC compiler and produced code for the Itanium architecture. We report the effectiveness of our method on 134 loop nests with 348 loop levels. Several strategies for register allocation are compared and analyzed.

On Optimizing a Class of Multi-Dimensional Loops with Reduction for Parallel Execution

This paper addresses the compile-time optimization of a form of nested-loop computation that is motivated by a computational physics application. The computations involve multi-dimensional surface and volume integrals where the integrand is a product of a number of array terms. Besides the issue of optimal distribution of the arrays among the processors, there is also scope for reordering of the operations using the commutativity and associativity properties of addition and multiplication, and the application of the distributive law to significantly reduce the number of operations executed. A formalization of the operation minimization problem and proof of its NP-completeness is provided. A pruning search strategy for determination of an optimal form is developed. An analysis of the communication requirements and a polynomial-time algorithm for determination of optimal distribution of the arrays are also provided.

Synchronization and communication costs of loop partitioning on shared-memory multiprocessor systems

The author presents strategies for static loop decomposition and scheduling as well as computer-assisted run-time scheduling that take into account, in addition to the cost of performing operations, the overhead costs associated with a decomposition and schedule. An algorithm for static decomposition of multidimensional loops based on the operation execution costs, communication costs, and synchronization costs is discussed. Synchronization instructions are introduced to ensure correct program execution following program decomposition. An algorithm for determining the explicit synchronization instruction that should be introduced to ensure correct execution of a program with arbitrarily nested loops is presented. Techniques for reducing run-time scheduling and communication and synchronization costs due to self-scheduling of multidimensional loops are also presented. Experiments performed on the Encore multiprocessor system demonstrate that the techniques developed can reduce overhead costs. >

Utilizing multidimensional loop parallelism on large scale parallel processor systems

Program parallelism and processor allocation issues for parallel processor systems are discussed. Optimal processor assignment algorithms are presented for simple and complex nested parallel loops. These processor assignment schemes can be used by the compiler to perform static processor allocation to multiply nested parallel loops. Speedup measurements for EISPACK and IEEE DSP subroutines that result from the optimal assignment of processors to parallel loops are also presented. These measurements indicate that optimal processor assignments result in almost linear speedups on parallel processor machines with a few tens of processes and significantly high speedups for machines with hundreds or thousands of processors.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>