Multi-core Research Articles

Embankment Breach Simulation and Inundation Mapping Leveraging High-Performance Computing for Enhanced Flood Risk Prediction and Assessment

Abstract. Embankment breaches represent significant hazards to communities and infrastructure, precipitating catastrophic flood occurrences. The precise prediction of floods and understanding the scope of inundation stemming from embankment failures are imperative for effective disaster preparedness and response. This research delves into a case study on simulating embankment breaches to evaluate the extent of flooding. Leveraging advanced hydrodynamic models validated through high-performance computing (HPC) systems, and integrating real-time data assimilation, we aim to improve accuracy in flood forecasting. The study endeavours to bolster flood risk management by furnishing detailed inundation maps and insights into embankment breach dynamics, thereby facilitating enhanced preparedness and response strategies. Our findings reveal that simulations conducted on multicore processors offer superior performance compared to single-core setups, yielding enhanced result accuracy and providing administrators with increased lead time. It unlocks high-resolution simulations for intricate basin details, explores a wider range of flood scenarios quickly, and allows for efficient ensemble modelling to assess model uncertainty. Through HPC utilization, we can harness high-resolution digital elevation models (DEMs) for 2D-hydrodynamic modelling, enabling rapid assessment of water spread resulting from embankment breaches within a mere 20-minute timeframe, a significant improvement from the previous 3–4 hours duration.

Tensor power flow formulations for multidimensional analyses in distribution systems

In this paper, we present two multidimensional power flow formulations based on a fixed-point iteration (FPI) algorithm to efficiently solve hundreds of thousands of Power flows (PFs) in distribution systems. The presented algorithms are the base for a new TensorPowerFlow (TPF) tool and shine for their simplicity, benefiting from multicore Central processing unit (CPU) and Graphics processing unit (GPU) parallelization. We also focus on the mathematical convergence properties of the algorithm, showing that its unique solution is at the practical operational point. The proof is validated using numerical simulations showing the robustness of the FPI algorithm compared to the classical Newton–Raphson (NR) approach. In the case study, a benchmark with different PF solution methods is performed, showing that for applications requiring a yearly simulation at 1-minute resolution, the computation time is decreased by a factor of 164, compared to the NR in its sparse formulation. Finally, a set of applications is described, highlighting the potential of the proposed formulations over a wide range of analyses in distribution systems.

A Parallel Tag Cache for Hardware Managed Tagged Memory in Multicore Processors

A Parallel Tag Cache for Hardware Managed Tagged Memory in Multicore Processors

Improved automated parallel implementation of GMM background subtraction on a multicore digital signal processor

<p><span>Scene segmentation is an essential step in a wide range of video processing applications, for instance, object recognition and tracking. The Gaussian mixture model (GMM) for background subtraction (BS) has gained widespread usage in scene segmentation, despite its known computational intensity. To tackle this challenge, we propose a practical solution to accelerate processing through a parallel implementation on an embedded multicore platform. In this paper, we present an improved automated parallel implementation of the GMM algorithm using the Orphan directive provided by open multiprocessing (OpenMP). Experimental assessments conducted on the eight cores of the C6678 digital signal processor (DSP) demonstrate significant advancements in parallel efficiency, particularly when handling high-resolution frames, including high-definition (HD) and full-HD resolutions. The achieved parallel efficiency surpasses the results obtained with classical OpenMP scheduling modes, encompassing dynamic, static, and guided approaches. Specifically, the parallel efficiency reaches approximately 82% for full-HD resolution frames and, 99.3% for low-resolution frames, respectively.</span></p>

Parallel Simulations of the Sharp Wave-Ripples of the Hippocampus on Multicore CPUs and GPUs

The simulation of realistic systems plays a crucial role in modern sciences. Complex organs such as the brain can be described by mathematical models to reproduce biological behaviors. In the brain, the hippocampus is a critical region for memory and learning. In the literature, a model to reproduce the memory consolidation mechanism has been proposed. This model exhibits a high degree of biological realism, though it is accompanied by a significant increase in computational complexity. This paper proposes the development of parallel simulation targeting different devices, namely multicore CPUs and GPUs. The experiments highlighted that the biological realism is maintained, together with a significant decrease of the processing times. Finally, the conducted analysis highlights that the GPU is one of the most suitable technologies for this kind of simulation.

On a Simplified Approach to Achieve Parallel Performance and Portability Across CPU and GPU Architectures

This paper presents software advances to easily exploit computer architectures consisting of a multi-core CPU and CPU+GPU to accelerate diverse types of high-performance computing (HPC) applications using a single code implementation. The paper describes and demonstrates the performance of the open-source C++ matrix and array (MATAR) library that uniquely offers: (1) a straightforward syntax for programming productivity, (2) usable data structures for data-oriented programming (DOP) for performance, and (3) a simple interface to the open-source C++ Kokkos library for portability and memory management across CPUs and GPUs. The portability across architectures with a single code implementation is achieved by automatically switching between diverse fine-grained parallelism backends (e.g., CUDA, HIP, OpenMP, pthreads, etc.) at compile time. The MATAR library solves many longstanding challenges associated with easily writing software that can run in parallel on any computer architecture. This work benefits projects seeking to write new C++ codes while also addressing the challenges of quickly making existing Fortran codes performant and portable over modern computer architectures with minimal syntactical changes from Fortran to C++. We demonstrate the feasibility of readily writing new C++ codes and modernizing existing codes with MATAR to be performant, parallel, and portable across diverse computer architectures.

Application-Level Evaluation of IEEE 802.1AS Synchronized Time and Linux for Distributed Real-Time Systems

The use of Ethernet and Linux is becoming common in industrial applications, even for those with real-time requirements, although neither of them were originally designed for this purpose. The emergence of Industry 4.0 (also known as Industrial Internet of Things, IIoT) has encouraged the evolution of these technologies to better handle real-time issues. On the one hand, Linux now supports mechanisms to configure certain real-time parameters, as well as core isolation and interrupt allocation facilities in multicore processors. On the other hand, the set of Ethernet standards IEEE 802.1 Time-Sensitive Networking (TSN) includes a high precision clock synchronization protocol (IEEE 802.1AS). The purpose of this work is to outline an execution framework for distributed systems based on TSN and Linux, which allows the execution of time-aware applications. We have studied and evaluated different configurations available for the proposed execution framework. In particular, a detailed characterization of the clock synchronization mechanism, from the application point of view, has been performed. Some conclusions about the current real-time capabilities of these technologies are also presented.

Performance Analysis of Spin Orbit Torque Magneto-Resistive RAM Caches in 4-core ARM Systems

Spin Orbit Torque Magnetic Random Access Memory (SOT–)MRAM is gaining interest as it eradicates several limitations posed by its predecessor Spin Transfer Torque (STT-)MRAM, yet inherits all its advantages. This work explores in detail, the suitability of SOT–MRAM implemented caches in different levels of memory hierarchy in comparison to conventional SRAM technology, over several performance parameters like area, energy consumption and execution time for an embedded benchmark suite. Our circuit-level analysis shows that SOT–MRAM outperforms SRAM for caches ([Formula: see text] KB), and only lags in area and read-access energy for smaller caches. A typical 512 KB SOT–MRAM cache improves area by 1%, read/write latency by 33/38%, and leakage by over 99% than that of SRAM memory technology. The architecture-level analysis confirms that on average SOT–MRAM is energy efficient by 74% in L1, 97.2% in L2 and 89.3% in both (i.e., L1 + L2) implementations against SRAM, for a 22[Formula: see text]nm technology node. We also estimate that SOT–MRAM only solution offers [Formula: see text]% energy savings and [Formula: see text]% better EDP than Hybrid (L1-SRAM and L2-SOT) memory hierarchy for multi-core ARM processors.

Construction of parallel algorithms for the study of complex systems objects with a hierarchical-network structure

The procedure for complexite evaluation of complex systems objects that have a hierarchical-network structure has been formalized.In order to realization this procedure in real time mode, parallel computation algorithms are proposed.Speed up estimates were obtained for the mentioned algorithms, which confirm their high efficiency. The proposed parallel algorithms are oriented for execution on modern computing means with shared and distributed memory: computers with multi-core processors, clusters, hybrid architectures and in high performance distributed environments.

NUMA-aware parallel sparse LU factorization for SPICE-based circuit simulators on ARM multi-core processors

In circuit simulators that resemble the Simulation Program with Integrated Circuit Emphasis (SPICE), one of the most crucial steps is the solution of numerous sparse linear equations generated by frequency domain analysis or time domain analysis. The sparse direct solvers based on lower-upper (LU) factorization are extremely time-consuming, so their performance has become a significant bottleneck. Despite the existence of some parallel sparse direct solvers for circuit simulation problems, they remain challenging to adapt in terms of performance and scalability in the face of rapidly evolving parallel computers with multiple NUMA hardware based on ARM architecture. In this paper, we introduce a parallel sparse direct solver named HLU, which re-examines the performance of the parallel algorithm from the viewpoint of parallelism in pipeline mode and the computing efficiency of each task. To maximize task-level parallelism and further minimize the thread waiting time, HLU devises a fine-grained scheduling method based on an elimination tree in pipeline mode, which employs depth-first search (DFS-like) to iteratively search for parent tasks and then place dependent tasks in the same task queue. HLU also suggests two NUMA node affinity strategies: thread affinity optimization based on NUMA nodes topology to guarantee computational load balancing and data affinity optimization to enable effective memory placement when threads access data. The rationality and effectiveness of the sparse solver HLU are validated by the SuiteSparse Matrix Collection. In comparison with KLU and NICSLU, the experimental results and analysis show that HLU attains a speedup of up to 9.14× and 1.26x (geometric mean) on a Huawei Kunpeng 920 Server, respectively.

Advancing SWAT Model Calibration: A U-NSGA-III-Based Framework for Multi-Objective Optimization

In recent years, remote sensing data have revealed considerable potential in unraveling crucial information regarding water balance dynamics due to their unique spatiotemporal distribution characteristics, thereby advancing multi-objective optimization algorithms in hydrological model parameter calibration. However, existing optimization frameworks based on the Soil and Water Assessment Tool (SWAT) primarily focus on single-objective or multiple-objective (i.e., two or three objective functions), lacking an open, efficient, and flexible framework to integrate many-objective (i.e., four or more objective functions) optimization algorithms to satisfy the growing demands of complex hydrological systems. This study addresses this gap by designing and implementing a multi-objective optimization framework, Py-SWAT-U-NSGA-III, which integrates the Unified Non-dominated Sorting Genetic Algorithm III (U-NSGA-III). Built on the SWAT model, this framework supports a broad range of optimization problems, from single- to many-objective. Developed within a Python environment, the SWAT model modules are integrated with the Pymoo library to construct a U-NSGA-III algorithm-based optimization framework. This framework accommodates various calibration schemes, including multi-site, multi-variable, and multi-objective functions. Additionally, it incorporates sensitivity analysis and post-processing modules to shed insights into model behavior and evaluate optimization results. The framework supports multi-core parallel processing to enhance efficiency. The framework was tested in the Meijiang River Basin in southern China, using daily streamflow data and Penman–Monteith–Leuning Version 2 (PML-V2(China)) remote sensing evapotranspiration (ET) data for sensitivity analysis and parallel efficiency evaluation. Three case studies demonstrated its effectiveness in optimizing complex hydrological models, with multi-core processing achieving a speedup of up to 8.95 despite I/O bottlenecks. Py-SWAT-U-NSGA-III provides an open, efficient, and flexible tool for the hydrological community that strives to facilitate the application and advancement of multi-objective optimization in hydrological modeling.

BIMSA: Accelerating Long Sequence Alignment Using Processing-In-Memory.

Recent advances in sequencing technologies have stressed the critical role of sequence analysis algorithms and tools in genomics and healthcare research. In particular, sequence alignment is a fundamental building block in many sequence analysis pipelines and is frequently a performance bottleneck both in terms of execution time and memory usage. Classical sequence alignment algorithms are based on dynamic programming and often require quadratic time and memory with respect to the sequence length. As a result, classical sequence alignment algorithms fail to scale with increasing sequence lengths and quickly become memory-bound due to data-movement penalties. Processing-In-Memory (PIM) is an emerging architectural paradigm that seeks to accelerate memory-bound algorithms by bringing computation closer to the data to mitigate data-movement penalties. This work presents BIMSA (Bidirectional In-Memory Sequence Alignment), a PIM design and implementation for the state-of-the-art sequence alignment algorithm BiWFA (Bidirectional Wavefront Alignment), incorporating new hardware-aware optimizations for a production-ready PIM architecture (UPMEM). BIMSA supports aligning sequences up to 100K bases, exceeding the limitations of state-of-the-art PIM implementations. First, BIMSA achieves speedups up to 22.24 × (11.95× on average) compared to state-of-the-art PIM-enabled implementations of sequence alignment algorithms. Second, achieves speedups up to 5.84 × (2.83× on average) compared to the highest-performance multicore CPU implementation of BiWFA. Third, BIMSA exhibits linear scalability with the number of compute units in memory, enabling further performance improvements with upcoming PIM architectures equipped with more compute units and achieving speedups up to 9.56 × (4.7× on average). Code and documentation are publicly available at https://github.com/AlejandroAMarin/BIMSA.

QArray: A GPU-accelerated constant capacitance model simulator for large quantum dot arrays

Semiconductor quantum dot arrays are a leading architecture for the development of quantum technologies. Over the years, the constant capacitance model has served as a fundamental framework for simulating, understanding, and navigating the charge stability diagrams of small quantum dot arrays. However, while the size of the arrays keeps growing, solving the constant capacitance model becomes computationally prohibitive. This paper presents an open-source software package able to compute a 100 × 100100×100 pixels charge stability diagram of a 16-dot array in less than a second. Smaller arrays can be simulated in milliseconds - faster than they could be measured experimentally, enabling the creation of diverse datasets for training machine learning models and the creation of digital twins that can interface with quantum dot devices in real-time. Our software package implements its core functionalities in the systems programming language Rust and the high-performance numerical computing library JAX. The Rust implementation benefits from advanced optimisations and parallelisation, enabling the users to take full advantage of multi-core processors. The JAX implementation allows for GPU acceleration.

Codebase release 1.3 for QArray

Semiconductor quantum dot arrays are a leading architecture for the development of quantum technologies. Over the years, the constant capacitance model has served as a fundamental framework for simulating, understanding, and navigating the charge stability diagrams of small quantum dot arrays. However, while the size of the arrays keeps growing, solving the constant capacitance model becomes computationally prohibitive. This paper presents an open-source software package able to compute a 100 × 100100×100 pixels charge stability diagram of a 16-dot array in less than a second. Smaller arrays can be simulated in milliseconds - faster than they could be measured experimentally, enabling the creation of diverse datasets for training machine learning models and the creation of digital twins that can interface with quantum dot devices in real-time. Our software package implements its core functionalities in the systems programming language Rust and the high-performance numerical computing library JAX. The Rust implementation benefits from advanced optimisations and parallelisation, enabling the users to take full advantage of multi-core processors. The JAX implementation allows for GPU acceleration.

Network-on-Chip (NoC) Applications for IoT-Enabled Chip Systems: Latest Designs and Modern Applications

Network-on-Chip (NoC) technology has emerged as a critical innovation in the field of integrated circuit design, addressing the growing demands for efficient, scalable, and high-performance on-chip communication. This review provides a comprehensive examination of NoC, highlighting its architecture, key features, and current applications. NoC leverages a network-based approach, utilizing routers and links to interconnect various components on a chip, thereby overcoming the limitations of traditional System-on-chip (SoC) architectures that rely on shared bus systems. The review underscores NoC’s superior communication efficiency, scalability, and reduced latency, which are essential for modern high-performance computing, multi-core processors, and advanced embedded systems. It also explores NoC’s ability to optimize power consumption through dynamic voltage scaling and power gating, making it a favorable choice for energy-efficient designs. Despite its complexity, NoC’s modularity and adaptability make it suitable for a wide range of applications, from artificial intelligence accelerators to high-performance data centers. In conclusion, NoC stands as a transformative technology that enhances the performance and scalability of integrated circuits, paving the way for more sophisticated and powerful electronic systems. As the demand for higher computational capabilities and efficiency continues to rise, NoC is poised to play an increasingly vital role in the advancement of electronic design and architecture.

The GPI sidechain of Toxoplasma gondii inhibits parasite pathogenesis.

Glycosylphosphatidylinositols (GPIs) are highly conserved anchors for eukaryotic cell surface proteins. The apicomplexan parasite, Toxoplasma gondii, is a widespread intracellular parasite of warm-blooded animals whose plasma membrane is covered with GPI-anchored proteins, and free GPIs called GIPLs. While the glycan portion is conserved, species differ in sidechains added to the triple mannose core. The functional significance of the Glcα1,4GalNAcβ1- sidechain reported in Toxoplasma gondii has remained largely unknown without understanding its biosynthesis. Here we identify and disrupt two glycosyltransferase genes and confirm their respective roles by serology and mass spectrometry. Parasites lacking the sidechain on account of deletion of the first glycosyltransferase, PIGJ, exhibit increased virulence during primary and secondary infections, suggesting it is an important pathogenesis factor. Cytokine responses, antibody recognition of GPI-anchored SAGs, and complement binding to PIGJ mutants are intact. By contrast, the scavenger receptor CD36 shows enhanced binding to PIGJ mutants, potentially explaining a subtle tropism for macrophages detected early in infection. Galectin-3, which binds GIPLs, exhibits an enhancement of binding to PIGJ mutants, and the protection of galectin-3 knockout mice from lethality suggests that Δpigj parasite virulence in this context is sidechain dependent. Parasite numbers are not affected by Δpigj early in the infection in wild-type mice, suggesting a breakdown of tolerance. However, increased tissue cysts in the brains of mice infected with Δpigj parasites indicate an advantage over wild-type strains. Thus, the GPI sidechain of T. gondii plays a crucial and diverse role in regulating disease outcomes in the infected host.IMPORTANCEThe functional significance of sidechain modifications to the glycosylphosphatidylinositol (GPI) anchor in parasites has yet to be determined because the glycosyltransferases responsible for these modifications have not been identified. Here we present identification and characterization of both Toxoplasmsa gondii GPI sidechain-modifying glycosyltransferases. Removal of the glycosyltransferase that adds the first GalNAc to the sidechain results in parasites without a sidechain on the GPI, and increased host susceptibility to infection. Loss of the second glycosyltransferase results in a sidechain with GalNAc alone, and no glucose added, and has negligible effect on disease outcomes. This indicates GPI sidechains are fundamental to host-parasite interactions.

Energy efficient permanence‐based community detection algorithm

SummaryDetecting an accurate community structure is a crucial task in network analysis. With the increasing popularity of social networking sites, it is essential to have a community detection algorithm that is not only efficien but also cost‐effective for running in data centers. There are several metrics for estimating the accuracy of community detection. However, previous research has shown that permanence, a vertex‐centric metric, provides the most precise estimate of a community structure compared to other approaches. Despite this, no study has been conducted on parallelizing a permanence‐based community detection algorithm and analyzing its energy efficiency. This article introduces Amoeba, a task parallel implementation of a permanence‐based community detection algorithm designed for multicore processors. It uses dynamic tasking to schedule the inherent irregular computation, and it can dynamically adapt the total number of parallel threads, which results in improved energy efficiency. We evaluated Amoeba using several real‐world and artificial graphs on a multicore server processor. Our experimental results show that Amoeba achieves a geometric mean speedup of 15.3 over its sequential implementation, and due to thread adaptability, it achieves energy savings of 12.4% and a speedup of 6% over its nonadaptive implementation.

Embedded IoT Design for Bioreactor Sensor Integration

This paper proposes an embedded Internet of Things (IoT) system for bioreactor sensor integration, aimed at optimizing temperature and turbidity control during cell cultivation. Utilizing an ESP32 development board, the system makes advances on previous iterations by incorporating superior analog-to-digital conversion capabilities, dual-core processing, and integrated Wi-Fi and Bluetooth connectivity. The key components include a DS18B20 digital temperature sensor, a TS-300B turbidity sensor, and a Peltier module for temperature regulation. Through real-time monitoring and data transmission to cloud platforms, the system facilitates advanced process control and optimization. The experimental results on yeast cultures demonstrate the system’s effectiveness at maintaining optimal growth, highlighting its potential to enhance bioprocessing techniques. The proposed solution underscores the practical applications of the IoT in bioreactor environments, offering insights into the improved efficiency and reliability of culture cultivation processes.

A novel molecularly imprinted solid phase based on SiO2-Ag2O double-nucleation doped with graphene oxide for extraction and determination of flavonoids from Acanthaceae ebracteatus via HPLC-MS/MS

(Objectives) A novel method was developed for extracting and determining flavonoids from marine mangrove medicinal plants. This approach utilizes surface molecular imprinting to increase selectivity. Graphene oxide doped with a SiO2–Ag2O dual core structure served as a scaffold for synthesizing multilayer surface-imprinted polymers. The surface of the SiO2-Ag2O@GO composite was modified through self-polymerization. (Methods) Acacetin molecularly imprinted polymers (AMIPs) were created via surface-initiated precipitation polymerization with acacetin as the template. These AMIPs were synthesized and characterized via ultraviolet (UV) spectroscopy, Fourier transform infrared (FT-IR) spectroscopy, scanning electron microscopy (SEM), X-ray diffraction (XRD), and transmission electron microscopy (TEM). Recycling experiments demonstrated the stability of the AMIPs. Analysis of the adsorption mechanism via the Langmuir and Freundlich models indicated that the Langmuir model was more suitable for predicting AMIPs. (Results) Scatchard plots showing two different binding sites of AMIPs for acacetin adsorption at various concentrations. The class selectivity of AMIPs for flavonoids was found in Acanthaceae ebracteatus. Compared with other analogs, competitive binding experiments revealed that the polymer had greater selectivity for acacetin. After AMIP solid-phase extraction (AMISPE), the linearity, LOD, LOQ, intraday and interday variabilities, recovery, and repeatability of AMIPs combined with HPLC–MS/MS were validated, confirming the method’s selectivity, precision, accuracy, and reproducibility. The contents of acacetin, apigenin, kaempferol, luteolin, quercetin, and genistein in Acanthaceae ebracteatus were determined. (Conclusions) These results indicate that AMISPE coupled with HPLC–MS/MS is a new, simple, and practical method for extracting, purifying, and enriching flavonoids from complex samples, such as those of herbs and other natural marine plants.

A new extension of the core inverse

There are a number of extensions of the core inverse represented by the products of known generalized inverses, like the core-EP inverse, DMP inverse, GC inverse and so on. However, none of them is an inner inverse of the matrix, and especially for an arbitrary nilpotent matrix, such inverses are always null. Our goal is to use a new technic to introduce an extension of the core inverse that preserves the interesting property of being an inner inverse of the matrix which need not necessarily be the null matrix of a nilpotent matrix. We define the extended core inverse for square complex matrices combining the sum and the difference of three known generalized inverses. Various properties and representations of the extended core inverse are developed. The extended dual core inverse is investigated too. We apply the extended core inverse to solve some systems of linear equations and one minimization problem. A significant normal equation related to least-squares solutions can be solved using the extended core inverse.