Multi-chip Architecture Research Articles

Design of an Integrated Power Module for Silicon Carbide MOSFET with Self-Compensation of the Magnetic Field

Compactness, efficiency, and light weight are the key topics in the design of power conversion systems for transportation applications. This demand is achievable by using wide band gap devices such as SiC devices, characterized by the high switching speed and low on-resistance. However, this trend imposes new challenges and the effect of parasitic elements of power package during switching transient becomes significant. Hence, new packaging solutions should be investigated for addressing this concern. This paper presents a new multichip power module architecture, where its design considering capacitive and inductive stray elements is carried out. Using Ansys Q3D Extractor, electromagnetic simulations are achieved to extract the inductive and capacitive parasitic element of one leg of a three-phase inverter.

Multi-chip front-end electronics LYRA for X and γ Ray detector for HERMES mission

We present the experimental results of the Application Specific Integrated Circuit (ASIC), called LYRA, specifically designed for the High-Energy Rapid Modular Ensemble of Satellites (HERMES) mission concept, a constellation of nano-satellites able to detect and localize high-energy rapid transient events (up to 2.2 MeV) as the Gamma Ray Bursts (GRBs) from the deep space. LYRA has been desied for the detection system composed by a combination of Gadolinium Aluminum Gallium Garnet (GAGG) scintillators for high-energy photons, coupled to a matrix of 120 silicon drift detectors (SDD), used for detecting both scintillation light and low-energy photons. The LYRA ASIC has been conceived with a multi-chip architecture: 120 LYRA Front-End chips (LYRA-FE) are placed in close proximity to the anodes of the SDD matrix for a first processing of the detector signals and trasmit them in current mode to four 32-channel LYRA Back-End chips (LYRA-BE) to complete the elaboration. The requirements that the LYRA ASIC have to fulfill for the HERMES project are challenging: the maximum input energy measured in Silicon must reach 120 keV — corresponding to 2.2 MeV on GAGG — with a linearity error below 1%, the electronic noise must be less then 30 el. r.m.s. and the power consumption less then 1 mW per channel in a system with 120 channels working in parallel. The characterization of LYRA has been carried out on a dedicated test board, coupling one channel of the ASIC with a 25 mm2 SDD. An input full scale range of 5.2 fC and an electronic noise of 22 el. r.m.s. have been measured at -33∘C with a power consumption of 745 µW per channel.

Author Correction: Scaling out Ising machines using a multi-chip architecture for simulated bifurcation

Author Correction: Scaling out Ising machines using a multi-chip architecture for simulated bifurcation

Scaling out Ising machines using a multi-chip architecture for simulated bifurcation

Scaling out Ising machines using a multi-chip architecture for simulated bifurcation

An Implementation of Multi-Chip Architecture for Real-Time Ray Tracing Based on Parallel Frame Rendering

In this paper, we propose a multi-chip architecture based on parallel frame rendering suitable for real-time ray tracing in dynamic scenes. In multi-chip architecture with the commonly used screen partitioning method, the acceleration structure data, such as a tree, updated in a dynamic scene must be transmitted to each chip. In the proposed frame division method, a tree build and ray tracing are performed on the same chip, and each frame is allocated to a predesignated multi-chip. Thus, the proposed method can achieve scalable performance improvement not only of ray tracing but also of a tree build. We implemented a multi-chip architecture on three field-programmable gate array (FPGA) boards and built 12 ray-tracing cores in the FPGA chip of each board. This configuration means that the inter-chip operates using the frame division method, while the inner chip operates using the screen partitioning method. The results of experiments showed that the proposed multi-chip architecture improved frames per second (FPS) performance by an average of 2.83 times compared to a single-chip architecture.

Scalable THz Network-On-Chip Architecture for Multichip Systems

While THz wireless network-on-chip (WiNoC) introduces considerably high bandwidth, due to the high path loss, it cannot be used for communication between far apart nodes, especially in a multichip architecture. In this paper, we introduce a cellular and scalable architecture to reuse the frequencies of the chips. Moreover, we use a novel structure called parallel-plate waveguide (PPW) that is suitable for interchip communication. The low-loss property of this waveguide lets us increase the number of chips. Each chip has a wireless node as a gateway for communicating with other chips. To shorten the length of intra- and interchip THz links, the optimum configuration is determined by leveraging the multiobjective simulating annealing (SA) algorithm. Finally, we compare the performance of the proposed THz multichip NoC with a conventional millimeter-wave one. Our simulation results indicate that when the system scales up from four to sixteen chips, the throughput of our design is decreased about 5.8 % , while for millimeter-wave NoC, this reduction is about 21 % . Furthermore, the average latency growth of our system is only 1 % compared with about 40 % increase for the millimeter-wave NoC.

A large-scale nesting ring multi-chip architecture for manycore processor systems

The optical network on chip (ONoC) paradigm has emerged as a promising solution to multi-core/many-core processor systems for offering enormous bandwidth and low power consumption. As chip multiprocessors (CMPs) scale to unprecedented numbers of cores, the performance of next-generation CMPs will be bounded by the process yield and power density of single chip. In earlier work we proposed a multi-chip ONoC architecture that scales to large numbers of CMPs and delivers high performance in terms of delay and throughout. Building on that work, in this paper we propose an optimized architecture for integrating a large number of cores into chips with a novel control strategy, including a contention resolution scheme and a resource reservation scheme. The proposed control strategy is crucial to large scale ONoCs, because the resource reservation scheme ensures efficient wavelength allocation for the traffic while the contention management scheme is effective in reducing the impact of contentions. To sustain good performance and energy efficiency of large-scale ONoC, the topology is optimized to reduce the average transmission distance with minimum increase of power consumption. We evaluate the proposed architecture within a 1000-core processor system and compare it with CMesh and several previously proposed topologies with different control strategies. The simulation results show that, our new large-scale architecture can achieve better performance on throughput and delay.

Nesting ring architecture of multichip optical network on chip for many-core processor systems

Optical network on chip (ONoC) is an attractive solution for multicore/many-core processor systems due to its high power efficiency and enormous bandwidth. However, as increasing numbers of cores need to be interconnected, the scalability of a many-core processor on a single chip is limited by its process yield and power density. A multichip architecture is, therefore, proposed to improve the scalability of ONoC. In multichip architectures, the throughput and traffic delay rely on both the intrachip and interchip networks. To exploit the advantages of multichip systems, first we propose a multichip ONoC architecture for a many-core processor system that employs a nesting ring topology. The design principles of multichip systems of different sizes are then investigated to achieve higher throughput and lower delay. These principles include the number of chips and the number of cores per chip, which are considered jointly for the first time. Finally, we evaluate the performance of the proposed architecture, implemented in 240-core and 400-core systems, respectively, and compare it to two other traditional ONoC architectures with respect to throughput and end-to-end (ETE) delay. The results show that the proposed multichip system exhibits good scalability, achieves high throughput, and provides low ETE delay.

The Die Embedded and RDL structure on the high density substrate (i-THOP®) for mobile application

Abstract The current trend in the electronics industry is one of increased computing performance, combined with a seemingly unending demand for portability and increased miniaturization; this is especially evident in the significant changes to the semiconductor device. To sustain the performance-improvement trend without increasing total cost, the partitioning of single die into a multi-chip architecture is widely studied in industry. These partitioned chips are then integrated into a single system-in-package (SiP). However, partitioning a single die into multiple split die causes two major challenges. The first is that it creates the need for very high density die to die interconnection. This interconnection is needed to provide enough routing density between the multiple die. Based on design studies, it believes that 2μm line and 2μm space is required in the package substrate. The second challenge is created by the increase in the overall die size. After partitioning the single die, each resulting smaller die must have its own I/O circuits, and effectively increases the total die area. This increase is a penalty, as mobile devices have a limited package size. When comparing a conventional package on package (PoP), the SiP requires a higher pin count with a finer pitch connection between the die and the memory. This finer pitch is needed to have enough I/Os, but within a limited package size to support mobile devices. To overcome these challenges, the structure of i-THOP® with POP pad, named “i-THOP® with Die embedded +ReDestribution Layer(RDL) structure”, has been developed. Herein, i-THOP® (integrated Thin film High density Organic Package) is a type of high-density substrate A key aspect to development of Die embedded +RDL is forming the multiple redistribution layers (RDL) over die and the fine pitch via connection. To achieve this, the proper material set was selected based on stress simulations and basic experiments. Regarding the manufacturing process, a conventional printed-circuit board (PCB) production line was used to minimize production cost. This article reports the manufacturing process and characteristics of the structure.

Concurrent Driving Method with Fast Scan Rate for Large Mutual Capacitance Touch Screens

A novel touch screen control technique is introduced, which scans each frame in two steps of concurrent multichannel driving and differential sensing. The proposed technique substantially increases the scan rate and reduces the ambient noise effectively. It is also extended to a multichip architecture to support excessively large touch screens with great scan rate improvement. The proposed method has been implemented using 0.18 μm CMOS TowerJazz process and tested with FPGA and AFE board connecting a 23-inch touch screen. Experimental results show a scan rate improvement of up to 23.8 times and an SNR improvement of 24.6 dB over the conventional method.

Smart electrode array device with CMOS multi-chip architecture for neural interface

A CMOS integrated flexible neural interface device has been designed and fabricated. The device enables electrical stimulation of neural tissues using an array of smart electrodes. The smart electrodes have versatile functions owing to the use of a dedicated CMOS microchip. These multiple smart electrodes also provide the array with sophisticated functions with only four wiring connections to external equipment. Moreover, the multi-chip architecture of the device is highly flexible and has low invasiveness to living body tissue. An in vivo evaluation of retinal stimulation was performed after implanting the device in the eye of an experimental animal. The stimulus function of the device was successfully demonstrated by observing responses in the visual cortex caused by the stimulation.

CMOS-Based Multichip Networked Flexible Retinal Stimulator Designed for Image-Based Retinal Prosthesis

We propose and characterize a CMOS LSI-based neural stimulator for retinal prosthesis technology. The stimulator is based upon a multichip architecture in which small-sized CMOS stimulators named ldquounit chipsrdquo are organized on a flexible substrate. We designed a unit chip with an on-chip stimulator and light-sensing circuitry. We verified that all the functions implemented on the unit chip worked correctly and that an organized unit chip can be used as a retinal stimulator with multisite image-based patterned stimulation. We also demonstrated light-controlled retinal stimulation for the first time in an <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">in vivo</i> animal experiment on a rabbit's retina.

A Multichip Neuromorphic System for Spike-Based Visual Information Processing

We present a multichip, mixed-signal VLSI system for spike-based vision processing. The system consists of an 80 x 60 pixel neuromorphic retina and a 4800 neuron silicon cortex with 4,194,304 synapses. Its functionality is illustrated with experimental data on multiple components of an attention-based hierarchical model of cortical object recognition, including feature coding, salience detection, and foveation. This model exploits arbitrary and reconfigurable connectivity between cells in the multichip architecture, achieved by asynchronously routing neural spike events within and between chips according to a memory-based look-up table. Synaptic parameters, including conductance and reversal potential, are also stored in memory and are used to dynamically configure synapse circuits within the silicon neurons.

CMOS LSI-based multichip flexible neural stimulation device with embedded bulk Pt electrodes

A CMOS LSI-based flexible neural stimulation device application with new fabrication technologies has been developed. The device was designed for application in retinal prosthesis. The device is based on multichip architecture, which enables the LSI-based stimulation device to be flexible. A fabrication process of arrayed bulk Pt electrodes, and a packaging structure of LSI chips with flip-chip bonding technology have been developed. These features provide the fabricated device with a lifetime of ten days in saline solution.

Flexible and extendible neural interface device based on cooperative multi-chip CMOS LSI architecture

An LSI-based cooperative multi-chip neural interface device, for stimulation as well as recording, is proposed and fabricated. The proposed multi-chip device consists of small (600 μm × 600 μm in the present design) intelligent neural interface unit chips. The unit chip has nine neural stimulation/recording electrodes and an individual control circuit. It can work not only as a stand-alone unit, but also in cooperation with other unit chips. One can configure any number of the unit chips as a multi-chip neural interface device. Compared to conventional single-chip architecture, the proposed multi-chip architecture has a number of advantages including thinness, mechanical strength, flexibility, and extendibility. That makes the multi-chip neural interface device more suitable for in vivo applications than conventional single-chip devices. Packaging technology for the multi-chip device was also developed. We developed a thin, flexible packaging technique for the multi-chip neural interface device and LSI-compatible Pt/Au stacked bump electrodes. The functions of the fabricated multi-chip neural interface device were characterized and the feasibility of the device as a random-access, multi-site stimulator was demonstrated.

Flexible and Extendible Neural Stimulation Device with Distributed Multichip Architecture for Retinal Prosthesis

We have proposed and designed a flexible and extendible neural stimulation device based on a distributed multichip architecture. The device is intended for retinal prosthesis application. A 4×4 array of small (600 µm×600 µm) unit chips was designed and fabricated with 0.6 µm standard complementary metal-oxide semiconductor (CMOS) technology. A package technology for a flexible retinal stimulation device has also been developed. We have demonstrated the function and feasibility of the device as a retinal stimulator in a saline environment.

A new architecture for digital time domain beamforming

This paper introduces a new approach to an architecture for digital time domain beamforming. The approach is unique as it produces sufficient beams to cover the observation space both simultaneously and continuously. Two implementation techniques are discussed; the first is a single chip beamformer based on a multibus architecture; the second is a multichip network-based architecture. The upper constraint on the number of sensors N, handled by a chip or chip set, is imposed by VLSI considerations. In both approaches, an additional chip has been identified which permits a number of systems, each supporting N sensors, to be combined to support larger numbers of sensors. The features of the architecture which permit this extension are the distributed memory and the reconfigurability of the modules. A two-dimensional FFT beamformer system performs a temporal FFT to separate out the frequencies and then performs a spatial FFT to determine the direction of the source(s) at specific frequencies. The beams produced by the new architecture contain all the signal frequencies which originate along the maximum response axis (MRA) of the beams. Therefore, an FFT may be performed on each beam to determine the frequencies of the signal sources. From this point of view, the new architecture eliminates the need for the temporal FFT required in the two-dimensional FFT beamformer. The processing power replaced by the architecture, assuming a system with 1024 beams, and a maximum signal frequency of 10 kHz, is 820 megafloating point operations per second (MFLOPS).