A new architecture for digital time domain beamforming

Abstract

This paper introduces a new approach to an architecture for digital time domain beamforming. The approach is unique as it produces sufficient beams to cover the observation space both simultaneously and continuously. Two implementation techniques are discussed; the first is a single chip beamformer based on a multibus architecture; the second is a multichip network-based architecture. The upper constraint on the number of sensors N, handled by a chip or chip set, is imposed by VLSI considerations. In both approaches, an additional chip has been identified which permits a number of systems, each supporting N sensors, to be combined to support larger numbers of sensors. The features of the architecture which permit this extension are the distributed memory and the reconfigurability of the modules. A two-dimensional FFT beamformer system performs a temporal FFT to separate out the frequencies and then performs a spatial FFT to determine the direction of the source(s) at specific frequencies. The beams produced by the new architecture contain all the signal frequencies which originate along the maximum response axis (MRA) of the beams. Therefore, an FFT may be performed on each beam to determine the frequencies of the signal sources. From this point of view, the new architecture eliminates the need for the temporal FFT required in the two-dimensional FFT beamformer. The processing power replaced by the architecture, assuming a system with 1024 beams, and a maximum signal frequency of 10 kHz, is 820 megafloating point operations per second (MFLOPS).