Multibit Trie Research Articles

PR-Trie: A Hybrid Trie with Ant Colony Optimization Based Prefix Partitioning for Memory-Efficient IPv4/IPv6 Route Lookup

Memory-efficient Internet Protocol (IP) lookup with high speed is essential to achieve link-speed packet forwarding in IP routers. The rapid growth of Internet traffic and the development of optical link technologies have made IP lookup a major performance bottleneck in core routers. In this paper, we propose a new IP route lookup architecture based on hardware called Prefix-Route Trie (PR-Trie), which supports both IPv4 and IPv6 addresses. In PR-Trie, we develop a novel structure called Overlapping Hybrid Trie (OHT) to perform fast longest-prefix-matching (LPM) based on Multibit-Trie (MT), and a hash-based level matching query used to achieve only one off-chip memory access per lookup. In addition, the proposed PR-Trie also supports fast incremental updates. Since the memory complexity in MT-based IP lookup schemes depends on the level-partitioning solution and the data structure used, we develop an optimization algorithm called Bitmap-based Prefix Partitioning Optimization (BP2O). The proposed BP2O is based on a heuristic search using Ant Colony Optimization (ACO) algorithms to optimize memory efficiency. Experimental results using real-life routing tables prove that our proposal has superior memory efficiency. Theoretical performance analyses show that PR-Trie outperforms the classical Trie-based IP lookup algorithms.

AGFT: Adaptive entries aggregation scheme to prevent overflow in multiple flow table environment

AbstractThe revolutionary architecture termed Software‐Defined Network provides flexible network management by detaching the control logic from the underlying data plane. The flow table resides in Ternary Content Addressable Memory imparts rules for the incoming flows with a limitation of high cost, limited storage, and consumes high power. In data center networks, when the traffic rate is high the overflow occurs due to storage limitation with high packet drop, frequent rule miss, and severe controller overhead. To overcome these challenges and to provide Quality of Service to the current network design sketch‐based entry reduction scheme is proposed. It incorporates three concurrent modules integrated to function sequentially where (1) Periodical analysis in Multiple Flow Tables is performed to ensure the availability of redundant entries using the robust data mining algorithm called Term Frequency. (2) Recurrent entries are further classified and clustered using the Boyer–Moore pattern matching algorithm to facilitate the forthcoming aggregation process. (3) A compact flow table is achieved with a customized multibit trie using Huffman coding compression technique. The experimental outcomes prove that this work prevents overflow by 99.98% with 98.99% enhanced flow table space and provides a significant reduction of controller overhead than the existing schemes.

IMT: A Memory-Efficient and Fast Updatable IP Lookup Architecture Using an Indexed Multibit Trie

IP address lookup is a function to determine nexthop for a given destination IP address. It takes an important role in modern routers because of its computation time and increasing Internet traffic. TCAM-based IP lookup approaches can exploit the capability of parallel searching but have a limitation of its size due to latency, power consumption, updatability, and cost. On the other hand, multibit trie-based approaches use SRAM which has relatively low power consumption and cost. They reduce the number of memory accesses required for each lookup, but it still needs several accesses. Moreover, the memory efficiency and updatability are proportional to the number of memory accesses. In this paper, we propose a novel architecture using an Indexed Multibit Trie (IMT) which is based on combined TCAM and SRAM. In the proposed architecture, each lookup takes at most two memory accesses. We present how the IMT is constructed so as to be memory-efficient and fast updatable. Experiment results with real-world forwarding tables show that our scheme achieves good memory efficiency as well as fast updatability.

A Multi-stage IPv6 Routing Lookup Algorithm Based on Hash Table and Multibit Trie

The address length of IPv6 is 128 and it has no classification addressing, which makes routing lookup processing burden of core router is heavier and the requirements are higher. As many existing algorithms cannot adapt to new requirements after expanding to IPv6, it is necessary to propose a new routing lookup algorithm based on IPv6. After thorough analysis of the IPv6 address prefix distribution regularity, this paper proposes a new scheme based on simple data structure: Hash Table and Multibit Trie (retrieval). This algorithm first classifies the prefix value and then starts its first lookup by using the first 48bits prefix of the IPv6 Address. Simulation results show that in most cases, the algorithm needs only one memory access to find the next hop routing information. This algorithm has high lookup speed and can be easily implemented with hardware.

An IPv6 Address Lookup Algorithm Based on Multi-bit Trie and Prefix Hierarchy

The size of IPv6 routing table growing rapidly, fast ip address lookup is becoming critical in high-speed packet forwarding. However, most of the IPv4 routing algorithm is not suitable for IPv6, *measure the characteristics of IPv6 and the routing table address prefix hierarchical distribution. In this paper, a new fast IP address lookup algorithm based on multi-bit trie and prefix hierarchy is proposed. The proposed algorithm has good scalability and effectively reduces the depth of the search tree.

Speeding up IP lookup procedure in software routers by means of parallelization

Performance of software routers is limited by the speed of operating system network protocol stack. A faster network protocol stack can be implemented in user space by utilizing parallelization and different optimization techniques. In this work we will demonstrate an efficient implementation of the IP lookup algorithm in user space with multibit trie structures. Afterwards, we will demonstrate the improvements achieved through parallelization based on the receive side scaling mechanism.

Multi-Stride Decision Trie for IP Address Lookup

Multi-bit tries have been proposed to improve the search performance of a binary trie by providing flexibility in stride values, which identify the number of bits examined at a time. However, constructing a variable-stride multi-bit trie is challenging since it is not easy to determine a proper stride value that satisfies the required performance at each node. The aim of this paper is to identify several desired characteristics of a trie for IP address lookup problems, and to propose a multi-stride decision trie that has these characteristics. Simulation results using actual routing sets with about 30,000 to 220,000 prefixes show that the proposed multi-stride decision trie has the desired characteristics and achieves IP address lookup using 33% to 47% of the 2-bit trie in the average number of node accesses, while requiring a smaller amount of memory.

LayeredTrees: Most Specific Prefix-Based Pipelined Design for On-Chip IP Address Lookups

Multibit trie-based pipelines for IP lookups have been demonstrated to be able to achieve the throughput of over 100 Gbps. However, it is hard to store the entire multibit trie into the on-chip memory of reconfigurable hardware devices. Thus, their performance is limited by the speed of off-chip memory. In this paper, we propose a new pipeline design called LayeredTrees that overcomes the shortcomings of the multibit trie-based pipelines. LayeredTrees pipelines the multi-layered multiway balanced prefix trees based on the concept of most specific prefixes. LayeredTrees is optimized to fit the entire routing table into the on-chip memory of reconfigurable hardware devices. No prefix duplication is needed and each ${\mbi {W}}$ -bit prefix is encoded in a (${\mbi {W}} + {\bf 1}$ )-bit format to save memory. Assume the minimal packet size is 40 bytes. Our experimental results on Virtex-6 XC6VSX315T FPGA chip show that the throughputs of 33.6 and 120.8 Gbps can be achieved by the proposed single search engine and multiple search engines running in parallel, respectively. Furthermore, the impact of update operations on the search performance is minimal. With the same FPGA device, an IPv6 routing table of 290,503 distinct entries can also be supported.

Data Structure Optimization for Power- Efficient IP Lookup Architectures

Power consumption has become a limiting factor in designing next generation network routers. Recent observation shows that IP lookup engines dominate the power consumption of core routers. Previous work on reducing power consumption of routers mainly focused on network- and system-level optimizations. This paper represents the first thorough study on the data structure optimization for lowering the power consumption in static random access memory (SRAM)-based IP lookup engines. Three different SRAM-based IP lookup architectures are discussed: nonpipelined, simple pipelined, and memory-balanced pipelined architectures. For each architecture, we formulate the problem of power minimization by revisiting the time-space tradeoff in multibit tries. Two distinct multibit trie algorithms are investigated: the expanded trie and the tree bitmap trie, which are widely used in SRAM-based IP lookup solutions. A theoretical framework is proposed to determine the optimal strides for building a multibit trie so that the worst-case power consumption of the IP lookup architecture is minimized. Experiments using real-life routing tables including both IPv4 and IPv6 data sets demonstrate that careful selection of strides in building the multibit tries can reduce the power consumption dramatically. We believe our methodology can be applied to other variants of multibit tries and can help in designing more power-efficient SRAM-based IP lookup architectures.

Recursively Partitioned Static IP Router Tables

We propose a method-recursive partitioning-to partition a static IP router table so that when each partition is represented using a base structure, such as a multibit trie or a hybrid shape shifting trie, there is a reduction in both the total memory required for the router table as well as in the total number of memory accesses needed to search the table. The efficacy of recursive partitioning is compared to that of the popular front-end table method to partition IP router tables. Our proposed recursive partitioning method outperformed the front-end method of all our test sets.

REFINE: The reconfigurable packet filtering on network processor

AbstractNetwork processors (NPs) are emerging as very promising platforms for developing reconfigurable and high‐performance network devices, due to their capability to combine the flexibility of general‐purpose processors with the high‐performance features of hardware‐based systems. They represent the most suitable solutions for implementing complex and dynamic tasks, such as packet classification and scheduling, which are key operations, for example, in DS networks. Programmability and reconfigurability allow NP‐based devices to be continuously adapted to the new network requirements, obtaining a high time in market.This paper illustrates the compound process that leads to the implementation of a reconfigurable multidimensional packet filtering on the Intel® IXP2400 NP. The multidimensional multibit trie is chosen as the best algorithm to be implemented and it is modified to exploit the specific features of NP. The different tasks are mapped on the NP computational resources and an optimized implementation is performed, with subsequent experimental validation. Copyright © 2008 John Wiley & Sons, Ltd.

AM-Trie: A Parallel Multidimensional Packet Classification Algorithm Fitting for Network Processor

Nowadays, many high speed Internet applications require high speed multidimensional packet classification algorithms. Based on the uniqueness of Network Processor, this paper presents a multidimensional classification algorithm—AM-Trie (asymmetrical multi-bit trie). AM-Trie is a high speed, parallel and scalable algorithm and very fit for the multi-thread and multi-core feature of the Network Processor. A heuristic field division algorithm is also presented, and it is proved theoretically that it can find out the minimum storage cost solution when the height of the AM-Tire is given. Finally, a prototype is implemented based on Intel IXP 2400 Network Processor. The performance testing result shows that AM-Trie is a high-speed and scalable algorithm; the throughput of the whole system is influenced little by the size of rules and it can reach 2.5 Gbps wire speed.

A Small and Fast IP Forwarding Table Using Hashing

Building next generation routers with the capability of forwarding multiple millions of packets per second is required for the increasing demand for high bandwidth on the Internet. Reducing the required memory size of the forwarding table is a possible solution since small forwarding table can be integrated into the application specific integrated circuit (ASIC). In this paper a hash technique is developed to reduce the size of the IP forwarding table. The proposed data structure is a compressed 8-8-8-8 multibit trie that is based on hash tables of 4-bit addresses. Two optimization techniques are also proposed to further improve the performance of the proposed schemes. Our experimental results show that the proposed hashing-based schemes are better than the Small Forwarding Table scheme [6] both in memory size and lookup latency.