Multi-bit Data Storage Research Articles

Flexible Multistate Data Storage Devices Fabricated Using Natural Lignin at Room Temperature.

The growing interest in bioinspired and sustainable electronics has induced research on biocompatible and biodegradable materials. However, conventional electronic devices have been restricted due to their nonbiodegradable and sometimes harmful and toxic materials, which can even cause environmental issues. Here, we report a resistive switching random access memory (ReRAM) device based on lignin, which is a biodegradable waste product of the paper industry. The active layer of the device can be easily formed using a simple solution process on a plastic substrate. The memory devices show stable bipolar resistive switching behavior with good endurance and retention. Appropriate control of the maximum reset voltage and compliance current can yield multibit data storage capability with at least four resistance states, which can be exploited to realize a high-density memory device. The resistive switching mechanism may be a result of formation and rupture of carbon-rich filaments. These results suggest that lignin is a promising candidate material for an inexpensive and environmentally benign ReRAM device. We believe that this study can initiate a new route toward development of biocompatible and flexible electronics.

Abnormal Multiple Charge Memory States in Exfoliated Few-Layer WSe2 Transistors.

To construct reliable nanoelectronic devices based on emerging 2D layered semiconductors, we need to understand the charge-trapping processes in such devices. Additionally, the identified charge-trapping schemes in such layered materials could be further exploited to make multibit (or highly desirable analog-tunable) memory devices. Here, we present a study on the abnormal charge-trapping or memory characteristics of few-layer WSe2 transistors. This work shows that multiple charge-trapping states with large extrema spacing, long retention time, and analog tunability can be excited in the transistors made from mechanically exfoliated few-layer WSe2 flakes, whereas they cannot be generated in widely studied few-layer MoS2 transistors. Such charge-trapping characteristics of WSe2 transistors are attributed to the exfoliation-induced interlayer deformation on the cleaved surfaces of few-layer WSe2 flakes, which can spontaneously form ambipolar charge-trapping sites. Our additional results from surface characterization, charge-retention characterization at different temperatures, and density functional theory computation strongly support this explanation. Furthermore, our research also demonstrates that the charge-trapping states excited in multiple transistors can be calibrated into consistent multibit data storage levels. This work advances the understanding of the charge memory mechanisms in layered semiconductors, and the observed charge-trapping states could be further studied for enabling ultralow-cost multibit analog memory devices.

Realization of resistive switching and magnetoresistance in ZnO/ZnO-Co composite materials.

Combining resistive switching and magnetoresistance in a system exhibits great potential for application in multibit nonvolatile data storage. It is in significance and difficulty to seek a material with resistances that can be stably switched at different resistance states modulated by an electrical field and a magnetic field. In this paper, we propose a novel electrode/ZnO/ZnO-Co/electrode device in which the storage layer combines a nanostructured ZnO-Co layer and a ZnO layer. The device exhibits bipolar resistive switching characteristics, which can be explained by the accumulation of oxygen vacancies due to the migration of oxygen ions by external electrical stimuli and the contribution of Co particles in the ZnO-Co layer. Moreover, the magnetoresistance effect at room temperature can be observed in the device at high and low resistance states. Therefore, through electrical and magnetic control, four resistance states are achieved in this system, presenting a new possibility towards enhancing data densities by many folds.

(Invited) Multi-Bit Transistor Memories Made from Mechanically Exfoliated WSe2 and Plasma-Doped MoS2

It is still desirable to explore new simple nano/microfabrication approaches that can create low-cost solid-state drives (SSDs) based on field-effect transistor (FET) memories. 2D semiconducting layered transition metal dichalcogenides (TMDCs, e.g., MoS2 and WSe2) are anticipated to provide new opportunities in this research area[1][2]. However, most recent efforts have been focused on the direct application of TMDC FET channels into the conventional FET-based memory structure consisting of regular floating gates, tunnel barriers, or charge trapping layers.[3][4] Such memory devices still have quite complicated architectures, and such works have not effectively reduced the complexity and cost of solid-state memory manufacturing. Recently, we found that an exfoliated multilayer MoS2 flake (Fig. 1a), after a plasma doping process, has a rough (or rippled) top layer (Fig. 1b). When incorporated into a FET structure (Fig. 1c), this rough layer can serve as a charge-trapping layer interfacing with the underlying pristine layers that serve as the FET channel. This device structure can function as a FET memory and enable multi-bit data storage (i.e., year-scale binary or 2-bit data storage; day-scale 3-bit data storage (see Fig. 1d)).2 This work has preliminarily leveraged the unique layered structure of TMDCs for making ultra-low-cost memory devices. Here, we further report that a mechanically exfoliated multilayer WSe2 flake can directly serve as a FET memory channel with no need of plasma doping and enable multi-bit data storage functionality. This finding could further simplify the fabrication steps for producing SSDs. The newly observed memory states in multilayer WSe2 are tentatively attributed to the vulnerability of WSe2 layers to mechanical exfoliation. This means that the mechanical exfoliation of a multilayer WSe2 flake from a bulk WSe2 stamp could directly result in a rough (or rippled) top layer on the exfoliated flake, as illustrated in Fig. 2a. Such a rough WSe2 top layer, similar to the plasma-doped MoS2 top layer illustrated in Fig. 1b, could serve as a charge-trapping layer for the FET memory and enable multi-bit data storage (Fig. 2b). Fig. 2c shows the retention characteristics of a set of 2-bit (i.e., 4 data levels) memory states measured from a representative WSe2 FET memory, which are comparable to the memory states obtained from a plasma-doped MoS2 FET memory (Fig. 1d). To support our hypothesis, we further characterized as-exfoliated WSe2 and MoS2 flakes using atomic force microscopy (AFM) (Fig. 3). The AFM results show that as-exfoliated multilayer WSe2 flakes exhibit a much larger surface roughness in comparison with as-exfoliated multilayer MoS2 flakes. Furthermore, the transmission electron micrograph (TEM) of exfoliated WSe2 layers exhibit clear Moire patterns, which implies the formation of rippled layers on top of mechanically exfoliated WSe2 flakes. These characterization results strongly support our hypothesis on the exfoliation-induced memory states in multilayer WSe2. Additional work will be performed to understand the physical origin of the vulnerability of WSe2 layers to mechanical exfoliation and evaluate the reliability/uniformity of multilayer WSe2 FET memories. In addition to advance the fabrication technology for producing low-cost memories, this work also provides important scientific insights for creating new nanoelectronic devices through mechanically processing emerging layered materials. [1] Sangwan, Vinod K, et al. Nature nanotechnology 10.5 (2015): 403-406. [2] Chen, Mikai, et al.ACS nano 8.4 (2014): 4023-4032. [3] Choi, Min Sup, et al. Nature communications 4 (2013): 1624. [4] Jariwala, Deep, et al. ACS nano 8.2 (2014): 1102-1120. Figure Captions: Figure 1: Illustrations of (a) an as-exfoliated multilayer MoS2 flake with a smooth top layer, (b) a plasma-doped MoS2 flake with a rough (or rippled) top layer, and (c) a FET memory with the plasma-doped MoS2 flake as the FET channel. (d) displays the retention characteristics of 2-bit data storage states in a typical FET memory made from a plasma-doped multilayer MoS2 flake. Figure 2: Illustrations of (a) an as-exfoliated multilayer WSe2 flake with a rough (or rippled) top layer, and (b) a FET memory with the exfoliated WSe2 flake as the FET channel. (c) displays the retention characteristics of 2-bit data storage states in a typical FET memory made from an as-exfoliated multilayer WSe2 flake. Figure 3: AFM images of the top surfaces of (a) an as-exfoliated multilayer WSe2 flake and (b) an as-exfoliated multilayer MoS2 flake. The WSe2 flake exhibits a much larger top surface roughness (RMS value: 5.6 nm) in comparison with the MoS2 flake (RMS value: 2.7 nm). Figure 4: TEM image of the top surfaces of an as-exfoliated multilayer WSe2 flake, which exhibits clear Moire patterns. Figure 1

Retention of intermediate polarization states in ferroelectric materials enabling memories for multi-bit data storage

A homogeneous ferroelectric single crystal exhibits only two remanent polarization states that are stable over time, whereas intermediate, or unsaturated, polarization states are thermodynamically instable. Commonly used ferroelectric materials however, are inhomogeneous polycrystalline thin films or ceramics. To investigate the stability of intermediate polarization states, formed upon incomplete, or partial, switching, we have systematically studied their retention in capacitors comprising two classic ferroelectric materials, viz. random copolymer of vinylidene fluoride with trifluoroethylene, P(VDF-TrFE), and Pb(Zr,Ti)O3. Each experiment started from a discharged and electrically depolarized ferroelectric capacitor. Voltage pulses were applied to set the given polarization states. The retention was measured as a function of time at various temperatures. The intermediate polarization states are stable over time, up to the Curie temperature. We argue that the remarkable stability originates from the coexistence of effectively independent domains, with different values of polarization and coercive field. A domain growth model is derived quantitatively describing deterministic switching between the intermediate polarization states. We show that by using well-defined voltage pulses, the polarization can be set to any arbitrary value, allowing arithmetic programming. The feasibility of arithmetic programming along with the inherent stability of intermediate polarization states makes ferroelectric materials ideal candidates for multibit data storage.

Electrophysical properties of Si/SiO2 nanostructures fabricated by direct bonding

The results of experimental investigation of diode n++–p++-Si structures, which were fabricated by direct bonding and have tunneling-thin SiO2 with Si nanoclusters embedded into the interface, are presented. The memristive effect with bipolar switching is demonstrated. The introduction of Si nanoclusters into the dielectric reduces the randomness of formation of a conducting channel. Intermediate metastable states are observed in the current–voltage characteristics. This may prove to be important for multibit data storage.

Nanoionic Resistive Switching Memories: On the Physical Nature of the Dynamic Reset Process

Resistive switching memories based on the valence change mechanism have attracted great attention due to their potential use in future nanoelectronics. The working principle relies on ion migration in an oxide matrix and subsequent nanoscale redox processes leading to a resistance change. While switching from a low resistive to a high resistive state, different intermediate resistance levels can be programmed by changing the maximum applied voltage, making resistive switches highly interesting for multibit data storage and neuromorphic applications. To date, this phenomenon, which is known as gradual reset, has been reported in various experimental studies, but a comprehensive physical understanding of this key phenomenon is missing. Here, a combined experimental and numerical modeling approach is presented to address these issues. Time‐resolved pulse measurements are performed to study the reset kinetics in TaOx‐based nano‐crossbar structures. The results are analyzed using a 2D dynamic model of nonisothermal drift–diffusion transport in the mixed electronic–ionic conducting oxide including the effect of contact potential barriers. The model accurately describes the experimental data and provides physical insights into the processes determining the gradual reset. The gradual nature can be attributed to the temperature‐accelerated oxygen‐vacancy motion being governed by drift and diffusion processes approaching an equilibrium situation.

Multibit Data Storage States Formed in Plasma-Treated MoS2 Transistors

New multibit memory devices are desirable for improving data storage density and computing speed. Here, we report that multilayer MoS2 transistors, when treated with plasmas, can dramatically serve as low-cost, nonvolatile, highly durable memories with binary and multibit data storage capability. We have demonstrated binary and 2-bit/transistor (or 4-level) data states suitable for year-scale data storage applications as well as 3-bit/transistor (or 8-level) data states for day-scale data storage. This multibit memory capability is hypothesized to be attributed to plasma-induced doping and ripple of the top MoS2 layers in a transistor, which could form an ambipolar charge-trapping layer interfacing the underlying MoS2 channel. This structure could enable the nonvolatile retention of charged carriers as well as the reversible modulation of polarity and amount of the trapped charge, ultimately resulting in multilevel data states in memory transistors. Our Kelvin force microscopy results strongly support this hypothesis. In addition, our research suggests that the programming speed of such memories can be improved by using nanoscale-area plasma treatment. We anticipate that this work would provide important scientific insights for leveraging the unique structural property of atomically layered two-dimensional materials in nanoelectronic applications.

Multibit Programmable Optoelectronic Nanowire Memory with Sub‐femtojoule Optical Writing Energy

Persistent challenges in the nanofabrication of optoelectronic memory elements with ready size‐scalability, multibit data storage, and ultralow optical writing energy have limited progress toward the construction of optical data storage/buffering elements in high‐density photonic‐electronic circuits. Here, a multibit programmable optoelectronic nanowire (NW) memory is described that operates with an ultralow optical writing energy [ca. 180 aJ bit−1 (ca. 330 photons bit−1)] and a low standby power consumption (<1 pW) at room temperature. In this system, photoionized charged defects behave as surface trapped charges to achieve the electrical memory effect. As a result of the high surface electric field, the rate of dissociation of the photoexcited charge is amplified, thereby decreasing the optical writing energy. Moreover, the extremely high dynamic photoconductive gain (ca. 1010) makes it possible to write multibit optical data bit‐by‐bit into the NW. These findings should open new opportunities in next‐generation multifunctional nanochips for optical data storage/buffering, optical data processing, and optical sensing purposes.

Spin memristive magnetic tunnel junctions with CoO-ZnO nano composite barrier

The spin memristive devices combining memristance and tunneling magnetoresistance have promising applications in multibit nonvolatile data storage and artificial neuronal computing. However, it is a great challenge for simultaneous realization of large memristance and magnetoresistance in one nanoscale junction, because it is very hard to find a proper spacer layer which not only serves as good insulating layer for tunneling magnetoresistance but also easily switches between high and low resistance states under electrical field. Here we firstly propose to use nanon composite barrier layers of CoO-ZnO to fabricate the spin memristive Co/CoO-ZnO/Co magnetic tunnel junctions. The bipolar resistance switching ratio is high up to 90, and the TMR ratio of the high resistance state gets to 8% at room temperature, which leads to three resistance states. The bipolar resistance switching is explained by the metal-insulator transition of CoO1−v layer due to the migration of oxygen ions between CoO1−v and ZnO1−v.

Conductance quantization in oxygen-anion-migration-based resistive switching memory devices

Quantized conductance was observed in an anion-migration-based resistive switching memory cell with the structure of (Ti, Ta, W)/Ta2O5/Pt. The conductance of the cell varies stepwise in units of single atomic conductance (77.5 μS), which is responsible for the formation and annihilation of atomic scale filament built from oxygen vacancies in Ta2O5 film. The quantized conductance behavior can be modulated by voltage pulses as fast as 100 ns. The demonstration of conductance quantization in Ta2O5 based memory device would open the door for quantized multi-bit data storage of anion-migration-based resistive switching nonvolatile memories.

A Novel Defect-Engineering-Based Implementation for High-Performance Multilevel Data Storage in Resistive Switching Memory

A novel strategy based on defect engineering is proposed for high-performance multibit data storage in oxide-based resistive random access memory (RRAM). Key innovations are: 1) material-oriented cell engineering for desired modification of physical locations of generated oxygen vacancies in resistive switching layer; and 2) operation scheme to control the amount of oxygen vacancy generated in the conducting filament regions during switching. Proper doping approach is applied to suppress the formation of oxygen vacancy clusters due to the avalanching effect in the forming and set processes. Gradual resistive switching process is observed in the devices with proper doping at the proper switching operation modes. Multilevels of resistance states are measured by the optimized dc or ac switching mode. Excellent memory performance with four-level data storage (good resistance uniformity under pulse switching, retention >10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">4</sup> s at 150°C, and endurance >10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">6</sup> cycles) is successfully demonstrated in hafnium oxide-based RRAM devices, indicating the viability of the proposed engineering design strategy. The proposed methodology helps to understand the mechanism of multilevel switching and provides guidelines for the design of high-performance multibit resistive switching memory devices.

Resistance switching in transparent magnetic MgO films

We have studied the abrupt and hysteretic changes of resistance in MgO-based capacitor devices. The switching behavior is discussed in terms of the formation and rupture of conduction filaments due to the migration of structural defects in the electric field, together with the redox events which affects the mobile carriers. The results presented in this paper suggest that MgO transparent films combining ferromagnetism and multilevel switching characteristics might pave the way for a new method for spintronic multibit data storage.

Resistance switching in electrodeposited polycrystalline Fe 3O 4 films

Resistance random access memory (RRAM) is an emerging nonvolatile memory that offers advantages of scalability, fast switching, and low voltages. Magnetite, Fe 3O 4, has been shown to exhibit resistance switching in nanoscale architectures such as superlattices. Here, we show that electrodeposited polycrystalline films of Fe 3O 4 exhibit multistate resistance switching. Experiments suggest that the insulator-to-metal transition may be facilitated by the presence of a thin nano-crystalline layer which is critical for resistance switching to occur at lower bias. We also show that the switching behavior can be tuned through the applied deposition potential. The multiple resistance states accessible in these simple architectures open up new possibilities for multi-bit data storage and retrieval.

Memristive switching of MgO based magnetic tunnel junctions

Here we demonstrate that both, tunnel magnetoresistance (TMR) and resistive switching (RS), can be observed simultaneously in nanoscale magnetic tunnel junctions. The devices show bipolar RS of 6% and TMR ratios of about 100%. For each magnetic state, multiple resistive states are created depending on the bias history, which provides a method for multibit data storage and logic. The electronic transport measurements are discussed in the framework of a memristive system. Differently prepared MgO barriers are compared to gain insight into the switching mechanism.