Multi-threaded Software Research Articles

Enhanced S2E for Analysis of Multi-Thread Software

Enhanced S2E for Analysis of Multi-Thread Software

Cross Layer Design Using HW/SW Co-Design and HLS to Accelerate Chaining in Genomic Analysis

DNA sequence analysis is a computationally intensive task. Minimap2 is a state-of-the-art software tool for third-generation sequence analysis workflow. Nearly 50% of Minimap2’s computation time is spent on what is known as the chaining step. In this paper, the chaining step is accelerated using a novel heterogeneous computing system combining an Intel FPGA-based hardware accelerator and a CPU (using HLS for the FPGA and multi-threaded software for the CPU). The system in this paper is capable of handling large realistic workloads, achieves up to ~1.35× performance improvement over the software solution running on an Intel CPU with SIMD intrinsics (Intel’s latest AVX-512), while consuming ~27% less energy. When compared to the software solution running on the CPU without SIMD intrinsics, the system performs ~1.9× faster while consuming ~38% less energy. Importantly, this work also ensures that the accuracy of the output generated is not compromised for the speed-up gained (this work only has an error rate of less than 10-6% compared to 26% in previous FPGA-based chaining step accelerator).

Software Methodology for Data Control and Collection for Autonomous Monitoring Systems with a Large Amount of Generated Information on the Example of Software for a Hydrological Radiolocation System

Introduction . The current data monitoring and collection systems produce a growing amount of generated information. Such factors, as the increasing sampling rate of ADCs and the increasing speed of systems for primary processing, receiving, and transmitting information, etc., make the systems operate almost at the bandwidth limit of data transmission interfaces. In some applications, such a flow is redundant and can be optimized through the use of various algorithms for the primary processing of information. However, in some applications, reducing the data flow is impossible, since the received information is processed with a delay. Therefore, the development of a software methodology for controlling and collecting data in the system of automatic monitoring of the sea surface by a hydrological radiolocation system seems a relevant research task. Aim . To synthesize a methodology and to develop software for controlling the information system of radar monitoring of the sea surface. Materials and methods . System approach, software architectural and algorithmic design, software quality management methods, system analysis, Qt framework, C++ programming language. Results . A working methodology for designing software for controlling information and measurement technologies with a large amount of generated data was obtained. The effectiveness of the methodology and software quality were confirmed by control tests. A 3-month autonomous testing of the stability and reliability of the system was carried out. Detection of data loss in the system comprised less than 0.002 %, thus not exceeding the specified critical level of 0.5 %. Conclusion . The developed methodology can be used in designing software for controlling information and measuring systems generating a large amount of data. The approaches used to build a multithread software architecture with asynchronous data flow control has shown their high efficiency.

A Low-Cost Hardware/Software Platform for Lossless Real-Time Data Acquisition from Imaging Spectrometers.

In real-time data-intensive applications, achieving real-time data acquisition from sensors and simultaneous storage with the necessary performance is challenging, especially if "no-data-lost" requirements are present. Ad hoc solutions are generally expensive and suffer from a lack of modularity and scalability. In this work, we present a hardware/software platform built using commercial off-the-shelf elements, designed to acquire and store digitized signals captured from imaging spectrometers capable of supporting real-time data acquisition with stringent throughput requirements (sustained rates in the boundaries of 100 MBytes/s) and simultaneous information storage in a lossless fashion. The correct combination of commercial hardware components with a properly configured and optimized multithreaded software application has satisfied the requirements in determinism and capacity for processing and storing large amounts of information in real time, keeping the economic cost of the system low. This real-time data acquisition and storage system has been tested in different conditions and scenarios, being able to successfully capture 100,000 1 Mpx-sized images generated at a nominal speed of 23.5 MHz (input throughput of 94 Mbytes/s, 4 bytes acquired per pixel) and store the corresponding data (300 GBytes of data, 3 bytes stored per pixel) concurrently without any single byte of information lost or altered. The results indicate that, in terms of throughput and storage capacity, the proposed system delivers similar performance to data acquisition systems based on specialized hardware, but at a lower cost, and provides more flexibility and adaptation to changing requirements.

Efficient real-time selective genome sequencing on resource-constrained devices.

Third-generation nanopore sequencers offer selective sequencing or "Read Until" that allows genomic reads to be analyzed in real time and abandoned halfway if not belonging to a genomic region of "interest." This selective sequencing opens the door to important applications such as rapid and low-cost genetic tests. The latency in analyzing should be as low as possible for selective sequencing to be effective so that unnecessary reads can be rejected as early as possible. However, existing methods that employ a subsequence dynamic time warping (sDTW) algorithm for this problem are too computationally intensive that a massive workstation with dozens of CPU cores still struggles to keep up with the data rate of a mobile phone-sized MinION sequencer. In this article, we present Hardware Accelerated Read Until (HARU), a resource-efficient hardware-software codesign-based method that exploits a low-cost and portable heterogeneous multiprocessor system-on-chip platform with on-chip field-programmable gate arrays (FPGA) to accelerate the sDTW-based Read Until algorithm. Experimental results show that HARU on a Xilinx FPGA embedded with a 4-core ARM processor is around 2.5× faster than a highly optimized multithreaded software version (around 85× faster than the existing unoptimized multithreaded software) running on a sophisticated server with a 36-core Intel Xeon processor for a SARS-CoV-2 dataset. The energy consumption of HARU is 2 orders of magnitudes lower than the same application executing on the 36-core server. HARU demonstrates that nanopore selective sequencing is possible on resource-constrained devices through rigorous hardware-software optimizations. The source code for the HARU sDTW module is available as open source at https://github.com/beebdev/HARU, and an example application that uses HARU is at https://github.com/beebdev/sigfish-haru.

Locating Side Channel Leakage in Time through Matched Filters

Side channel attacks provide an effective way to extract secret information from the execution of cryptographic algorithms run on a variety of computing devices. One of the crucial steps for a side channel attack to succeed is the capability to locate the time instant in which the cryptographic primitive being attacked is effectively leaking information on the side channel itself, and synchronize the data obtained from the measurements on that instant. In this work, we propose an efficient and effective solution relying on the digital signal processing technique known as matched filters. We derive our matched filter with a small amount of profiling information which can be obtained from a device matching the one under attack. Our technique reliably identifies the cryptographic operation being computed, even when system interrupts or software multithreading are enabled on our target platform. We validate our approach through a successful attack against an unprotected AES implementation running on a Cortex-M4-based microcontroller.

Co-Design of Multicore Hardware and Multithreaded Software for Thread Performance Assessment on an FPGA

Multicore and multithreaded architectures increase the performance of computing systems. The increase in cores and threads, however, raises further issues in the efficiency achieved in terms of speedup and parallelization, particularly for the real-time requirements of Internet of things (IoT)-embedded applications. This research investigates the efficiency of a 32-core field-programmable gate array (FPGA) architecture, with memory management unit (MMU) and real-time operating system (OS) support, to exploit the thread level parallelism (TLP) of tasks running in parallel as threads on multiple cores. The research outcomes confirm the feasibility of the proposed approach in the efficient execution of recursive sorting algorithms, as well as their evaluation in terms of speedup and parallelization. The results reveal that parallel implementation of the prevalent merge sort and quicksort algorithms on this platform is more efficient. The increase in the speedup is proportional to the core scaling, reaching a maximum of 53% for the configuration with the highest number of cores and threads. However, the maximum magnitude of the parallelization (66%) was found to be bounded to a low number of two cores and four threads. A further increase in the number of cores and threads did not add to the improvement of the parallelism.

Adjustable shunt-current intensity circuit and system for current conduction treatment of epilepsy

In this paper, we developed a shunt-current intensity self-adjustable closed-loop control circuit system for current conduction treatment in temporal lobe epilepsy. To examine the dose-response relationship between conductive intensity and therapeutic outcomes of current conduction treatment, the control system consists of neural signal recording module for high-speed data rate acquisition, signal amplification and pre-processing, current shunt module for current conduction, data transmission and control module for real-time data communication with the personal computer and on-off of current conduction. Multithread and queue software architecture was implemented to ensure real-time data transmission, display and analysis by LabVIEW software. Results indicate that the input noise of the system is less than 2 [Formula: see text]Vrms, signal frequency bandwidth range is 1 Hz[Formula: see text]10 kHz, and the shunt-current detection range is 0.1–3000 [Formula: see text]A with the accuracy of above 99.985%, meeting the requirements for the detection of neural electrophysiological signal and the research on the dose-response relationship between conductive intensity and therapeutic outcomes of electronic conduction treatment.

Implementation of a Multi-Word Compare-and-Swap Operation without Garbage Collection

With the rapid increase in the number of CPU cores, software that can utilize these many cores is required. A lock-free algorithm based on compare-and-swap (CAS) operations is one of the concurrency control methods to implement such multi-threading software. A multi-word CAS (MwCAS) operation is an extension of a CAS operation to swap multiple words atomically. However, we noticed that the performance of the existing MwCAS implementation is limited because of garbage collection even if in a low-contention environment. To achieve high performance in low-contention workloads, we propose a new MwCAS algorithm without garbage collection. Experimental results show that our approach is three to five times faster than implementation with garbage collection in low-contention workloads. Moreover, the performance of the proposed method is also superior in a high-contention environment.

THE RUNTIME ANALYSIS OF COMPUTATION OF MODULAR EXPONENTIATION

Context. Providing the problem of fast calculation of the modular exponentiation requires the development of effective algorithmic methods using the latest information technologies. Fast computations of the modular exponentiation are extremely necessary for efficient computations in theoretical-numerical transforms, for provide high crypto capability of information data and in many other applications.
 Objective – the runtime analysis of software functions for computation of modular exponentiation of the developed programs based on parallel organization of computation with using multithreading.
 Method. Modular exponentiation is implemented using a 2k-ary sliding window algorithm, where k is chosen according to the size of the exponent. Parallelization of computation consists in using the calculation of the remainders of numbers raised to the power of 2i modulo, and their further parallel multiplications modulo.
 Results. Comparison of the runtimes of three variants of functions for computing the modular exponentiation is performed. In the algorithm of parallel organization of computation with using multithreading provide faster computation of modular exponentiation for exponent values larger than 1K binary digits compared to the function of modular exponentiation of the MPIR library. The MPIR library with an integer data type with the number of binary digits from 256 to 2048 bits is used to develop an algorithm for computing the modular exponentiation with using multithreading.
 Conclusions. In the work has been considered and analysed the developed software implementation of the computation of modular exponentiation on universal computer systems. One of the ways to implement the speedup of computing modular exponentiation is developing algorithms that can use multithreading technology on multi-cores microprocessors. The multithreading software implementation of modular exponentiation with increasing from 1024 the number of binary digit of exponent shows an improvement of computation time with comparison with the function of modular exponentiation of the MPIR library.

NGSremix: a software tool for estimating pairwise relatedness between admixed individuals from next-generation sequencing data.

Estimation of relatedness between pairs of individuals is important in many genetic research areas. When estimating relatedness, it is important to account for admixture if this is present. However, the methods that can account for admixture are all based on genotype data as input, which is a problem for low-depth next-generation sequencing (NGS) data from which genotypes are called with high uncertainty. Here, we present a software tool, NGSremix, for maximum likelihood estimation of relatedness between pairs of admixed individuals from low-depth NGS data, which takes the uncertainty of the genotypes into account via genotype likelihoods. Using both simulated and real NGS data for admixed individuals with an average depth of 4x or below we show that our method works well and clearly outperforms all the commonly used state-of-the-art relatedness estimation methods PLINK, KING, relateAdmix, and ngsRelate that all perform quite poorly. Hence, NGSremix is a useful new tool for estimating relatedness in admixed populations from low-depth NGS data. NGSremix is implemented in C/C++ in a multi-threaded software and is freely available on Github https://github.com/KHanghoj/NGSremix.

Robotic laser sensing and laser mirror excitation for pulse-echo scanning inspection of fixed composite structures with non-planar geometries

This paper proposes a system for a laser ultrasonic inspection of fixed non-planar composite structures. A pulse-echo configuration is used by which both the sensing and excitation lasers hit the same point on the structure, utilizing bulk waves for a through-the-thickness defect evaluation. A high signal-to-noise ratio is ensured by mounting a laser Doppler vibrometer (LDV), used as the sensing laser, on a 6 degree-of-freedom robot arm, thus allowing the correct distance and angle of the laser incident on the inspected structure to be maintained throughout the scan. The excitation laser is steered separately through a laser mirror scanner (LMS) to keep the robot payload sufficiently low, allowing the use of a lightweight portable robot arm. This robot arm can be mounted on a moveable platform suitable for in-situ inspections. An RGB-D camera is used for imaging the structure in front of the system, and a scan area with the required size can be delimited on the image produced by the camera. A scan path for the robot arm and laser mirror scanner is automatically generated by keeping the shape and distance of the structure within the delimited scan area. A graphical user interface allows the control of all individual blocks and contains the necessary algorithms for image capture of a specimen, geometry calculations, scan-path generation, signal acquisition, signal processing, and display of the results. This is a multithreaded software, ensuring a fast calculation of the structural geometry and scan path prior to the inspection and real-time updating of the results during the inspection. Composite specimens consisting of radial and conic sections with subsurface defects were inspected using the system. The test results show that the system is extremely reliable in detecting defects, particularly in the non-planar parts of the specimen.

Verified secure compilation for mixed-sensitivity concurrent programs

Abstract Proving only over source code that programs do not leak sensitive data leaves a gap between reasoning and reality that can only be filled by accounting for the behaviour of the compiler. Furthermore, software does not always have the luxury of limiting itself to single-threaded computation with resources statically dedicated to each user to ensure the confidentiality of their data. This results in mixed-sensitivity concurrent programs, which might reuse memory shared between their threads to hold data of different sensitivity levels at different times; for such programs, a compiler must preserve the value-dependent coordination of such mixed-sensitivity reuse despite the impact of concurrency. Here we demonstrate, using Isabelle/HOL, that it is feasible to verify that a compiler preserves noninterference, the strictest kind of confidentiality property, for mixed-sensitivity concurrent programs. First, we present notions of refinement that preserve a concurrent value-dependent notion of noninterference that we have designed to support such programs. As proving noninterference-preserving refinement can be considerably more complex than the standard refinements typically used to verify semantics-preserving compilation, our notions include a decomposition principle that separates the semantics preservation from security preservation concerns. Second, we demonstrate that these refinement notions are applicable to verified secure compilation, by exercising them on a single-pass compiler for mixed-sensitivity concurrent programs that synchronise using mutex locks, from a generic imperative language to a generic RISC-style assembly language. Finally, we execute our compiler on a non-trivial mixed-sensitivity concurrent program modelling a real-world use case, thus preserving its source-level noninterference properties down to an assembly-level model automatically. All results are formalised and proved in the Isabelle/HOL interactive proof assistant. Our work paves the way for more fully featured compilers to offer verified secure compilation support to developers of multithreaded software that must handle data of multiple sensitivity levels.

Improved fast phase unwrapping algorithm based on parallel acceleration

Aiming at the shortcoming of low serial operational efficiency in the quality-map-guided phase-unwrapping algorithm proposed by Miguel, an improved algorithm for parallel merging of multiple low-reliability blocks is pro-posed. Under the condition that the original algorithm design idea is satisfied, the unwrapping path is redefined as the largest reliable edge of the block. In addition, based on the non-continuous characteristic of the unwrapping path of the original algorithm, a low-reliability block out-of-order merging strategy is proposed to make multiple merging tasks can be performed simultaneously. The improved algorithm uses a multi-threaded software architecture. The main thread is responsible for looping through the unprocessed blocks to check whether they meet the requirements of merging, and the child threads receive and perform the merge tasks. The experimental results show that the improved method is completely consistent with the processing results of the original algorithm, and the parallel improvement strategy can effectively use the computer's multi-core resources, so that the operational efficiency of the phase unwrapping algorithm is improved by more than 50%.

FPGA Accelerated Analysis of Boolean Gene Regulatory Networks.

Boolean models are a powerful abstraction for qualitative modeling of gene regulatory networks. With the recent availability of advanced high-throughput technologies, Boolean models have increasingly grown in size and complexity, posing a challenge for existing software simulation tools that have not scaled at the same speed. Field Programmable Gate Arrays (FPGAs) are powerful reconfigurable integrated circuits that can offer massive performance improvements. Due to their highly parallel nature, FPGAs are well suited to simulate complex molecular networks. We present here a new simulation framework for Boolean models, which first converts the model to Verilog, a standardized hardware description language, and then connects it to an execution core that runs on an FPGA coherently attached to a POWER8 processor. We report an order of magnitude speedup over a multi-threaded software simulation tool running on the same processor on a selection of Boolean models. Analysis on a T-cell large granular lymphocyte leukemia (T-LGL) demonstrates that our framework achieves consistent performance improvements resulting in new biological insights. In addition, we show that our solution allows to perform attractor detection at an unprecedented speed, exhibiting a speedup ranging from one to three orders of magnitude compared to alternative software solutions.

Testing of multithreaded applications with locks on non-atomic variables

Subject of Research. The paper presents the study of fuzz testing algorithm for “data race” type fault finding in multithreaded software. The algorithm is implemented in the Google TSan tool. The disadvantage of the studied algorithm is the inability to test software products which use non-atomic variables. At this, the use of such tool is excluded for testing of modern applications that implement joint access of program streams to data. We propose a new algorithm for fuzz testing of multithreaded applications and a method for its implementation in the fuzz testing module of the Google TSan tools. Method. Various combinations of the execution of program streams are the input data in the process of fuzz testing of multithreaded applications. The proposed method of fuzz testing for multithreaded software applications assumes that errors in multithreaded applications manifest themselves only at the threads switching points, also called synchronization points. The thread scheduler is implemented as simply as possible. Each thread is assigned with a status marker tracking its activity during the program running. A thread can be in an unknown state (until the first synchronization point), in a state of execution, in a state of waiting in a queue for execution, as well as in a state where the thread has spent its execution quantum but has not reached the synchronization point. Such thread state is automatically changed to the state of waiting at the synchronization point. Thread control is carried out using a separate program thread that monitors the status of all threads and exposes the corresponding marker to the threads that have spent the execution quantum. The error search mechanism is implemented in the software product at the compilation stage by specifying the appropriate options. Main Results. A new fuzz testing module has been integrated in the Google TSan tool, which finds “data race” errors in any multithreaded applications, both with synchronization of access to shared data and with shared access to data. Practical Relevance. Verification of multithreaded software with shared access to data, in particular case of applying non-atomic variables, is especially relevant for the heavily loaded scalable software systems.

ATLAS High Level Trigger within the multi-threaded software framework AthenaMT

Athena is the software framework used in the ATLAS experiment throughout the data processing path, from the software trigger system through offline event reconstruction to physics analysis. The shift from high-power single-core CPUs to multi-core systems in the computing market means that the throughput capabilities of the framework have become limited by the available memory per process. For Run 2 of the Large Hadron Collider (LHC), ATLAS has exploited a multi-process forking approach with the copy-on-write mechanism to reduce the memory use. To better match the increasing CPU core count and, therefore, the decreasing available memory per core, a multi-threaded framework, AthenaMT, has been designed and is now being implemented. The ATLAS High Level Trigger (HLT) system has been remodelled to fit the new framework and to rely on common solutions between online and offline software to a greater extent than in Run 2. We present the implementation of the new HLT system within the AthenaMT framework, which is going to be used in ATLAS data-taking during Run 3 (2021 onwards) of the LHC. We also report on interfacing the new framework to the current ATLAS Trigger and Data Acquisition (TDAQ) system, which aims to bring increased flexibility whilst needing minimal modifications to the current system. In addition, we show some details of architectural choices which were made to run the HLT selection inside the ATLAS online dataflow, such as the handling of the event loop, returning of the trigger decision and handling of errors.

The FELIX detector interface for the ATLAS TDAQ upgrades and its deployment in the ITk demonstrator setup

The ATLAS experiment at the LHC at CERN will move to use the Front-End Link eXchange (FELIX) system in a staged approach for LHC Run 3 (2021) and LHC Run 4 (2026). FELIX will act as the interface between the data acquisition; detector control and TTC (Timing, Trigger and Control) systems; and new or updated trigger and detector front-end electronics. FELIX functions as a router between custom serial links from front end ASICs and FPGAs to data collection and processing components via a commodity switched network. Links may aggregate many slower links or be a single high bandwidth link. FELIX also forwards the LHC bunch-crossing clock, fixed latency trigger accepts and resets received from the TTC system to front-end electronics. The FELIX system uses commodity server technology in combination with FPGA-based PCIe I/O cards. The FELIX servers run a software routing platform serving data to network clients. Commodity servers connected to FELIX systems via the same network run innovative multi-threaded software for event fragment building, processing, buffering and forwarding. This proceeding will describe the design and status of the FELIX based readout for the Run 3 upgrade, during which a subset of the detector will be migrated. It will also show how the same concept has been successfully introduced into the demonstrator test bench of the ATLAS Pixel Inner Tracker, acting as a proof of concept towards the longer term Run 4 upgrade in which all detectors will adopt a FELIX based readout.

A Deadlock Prevention Policy for a Class of Multithreaded Software

Deadlock is an undesired situation in multithreaded software since it can lead to the stoppage of software. This paper studies the problem of deadlock control of multithreaded software based on Gadara nets, which are well studied for modelling concurrent programs. In particular, an iterative deadlock prevention policy based on siphons is proposed for a class of ordinary Gadara nets where the initial marking of each idle place is one. At each iteration, we compute emptiable siphons containing the smallest number of resource places. Then, bad markings are computed based on these siphons. On the basis of the bad markings, a constraint is constructed that forbids not only bad markings that empty one of the siphons but also some other bad markings. The algorithm is carried out until no emptiable siphon exists in the net. Compared with the existing methods, the resultant net derived from the proposed method is live and maximally permissive with a simpler supervisor. Finally, two examples are provided to illustrate the proposed deadlock prevention policy.

Load Balancing for Stateful Forwarding by Mitigating Heavy Hitters: A Case for Multi-Threaded NDN Software Routers

Equal load balancing for dispatching incoming packets to multiple threads is a crucial requirement in the stateful forwarding of multi-threaded software routers to achieve high-speed forwarding and low packet loss simultaneously. However, equal load balancing is not trivial for Named Data Networking (NDN) routers because of their stateful forwarding. In other words, the consistency of flow states should be maintained so that multiple threads do not access the states simultaneously. Sharding, wherein packets of the same flow are dispatched to the same thread while keeping loads of threads equal, has been proposed; however, in this study, we reveal that heavy hitters like popular content packets cause load imbalance, which may eventually cause packet losses. This study proposes a load balancing mechanism for NDN routers by exploiting the fact that states of flows need not be rigorously maintained when content packets are returned from caches at intermediate routers.