Multi-thread Method Research Articles

A Dual-Shader 3-D Graphics Processor With Fast 4-D Vector Inner Product Units and Power-Aware Texture Cache

This paper presents a fully programmable 3-D graphics processor using unified shaders for mobile environment. In the system level, we adopted dual-core, dual-issue VLIW, and multithreading methods to utilize instruction, data, and task level parallelism in the graphics applications. In the shader core level, a novel IEEE-754 compliant 4-D vector inner product arithmetic unit and a configurable texture cache are proposed. Using these methods, the proposed processor achieves 143 Mvertices/s and 2.3 Gtexels/s consuming the power of 367 mW. The evaluation shows significant performance and power-delay product benefits. For real graphics applications, test results indicate 2.07 times improvement in performance and 34% reduction in power-delay product compared to previous mobile 3-D graphics processors. The proposed 3-D graphics processor is implemented in 4.5× 4.52 mm using 0.18 μm CMOS technology.

Complete Pattern Matching for DNA Computing

Pattern matching is essential in many applications such as information retrieval, logic programming, theorem-proving, term rewriting and DNA-computing. It usually breaks down into two categories: root and complete pattern matching. Root matching determines whether a subject term is an instance of a pattern in a pattern set while complete matching determines whether a subject term contains a sub-term that is an instance of a pattern in a pattern set. For the sake of efficiency, root pattern matching need to be deterministic and lazy. Furthermore, complete pattern matching also needs to be parallel. Unlike root pattern matching, complete matching received little interest from the researchers of the field. In this paper, we present a novel deterministic multi-threaded complete matching method. This method subsumes a deterministic lazy root matching technique that was developped by the authors in an earlier work. We evaluate the performance of proposed method using theorem-proving and DNA-computing applications.

An Effective Configuration Method for Java-Internet Computing Environment

For a distributed parallel computing platform with multiple computers connected to the Internet, Java-Internet Computing Environment (JICE) is designed with multithreading and remote method invocation (RMI) mechanisms provided in Java. In general, the performance of communication on parallel applications causes a significant impact on the overall performance under network-based environment. To decrease communication time that is a bottleneck of performance enhancement, a method of system configuration, called as a grouping, is proposed. Grouping is how to divide a set of distributed nodes into several working groups based on the optimal communication time. Performance of grouping is evaluated through the analysis of communication time under JICE, and verified through the simulation. According to the analysis, the effective number of groups can be determined depending on the ratio of shared memory write references. Grouping can enhance the performance of JICE about 2∼ 3 times in those applications with a reasonably high ratio of shared memory references.