Multi-stage Noise Shaping Research Articles

A fully integrated multi-standard frequency synthesizer for GNSS receivers with cellular network positioning capability

A fully integrated hybrid integer/fractional frequency synthesizer is presented. With a single multiband voltage-controlled-oscillator (VCO), the frequency synthesizer can support GPS, Galileo, Compass and TD-SCDMA standards. Design is carefully performed to trade off power, die area and phase noise performance. By reconfiguring between the integer mode and fractional mode, different frequency resolution requirements and a constant loop bandwidth for each standard can be achieved simultaneously. Moreover, a long sequence length, reduced hardware complexity multi-stage-noise-shaping (MASH) Δ−Σ modulator is employed to reduce fractional spur in the fractional mode. Fabricated in a 0.18 μm CMOS technology, the frequency synthesizer occupies an active area of 1.48 mm2 and draws a current of 13.4–16.2 mA from a 1.8 V power supply. The measured phase noise is lower than −80 dBc/Hz at 100 kHz offset and −113 to −124 dBc/Hz at 1 MHz offset respectively, while the measured reference spur is −71 dBc in integer mode and the fractional spur is −65 dBc in fractional mode.

Hardware Reduction in Digital Delta-Sigma Modulators via Bus-Splitting and Error Masking—Part II: Non-Constant Input

In this two-part paper, a design methodology for hardware reduction in digital delta-sigma modulators (DDSMs) based on bus-splitting and error masking is presented. Part I addresses Multi stAge noise SHaping (MASH) DDSMs with constant inputs; Part II focuses on error feedback modulators (EFMs) with time-varying inputs. In this paper, we address EFMs with DC inputs plus additive input least significant bit (LSB) dithering and show how hardware reduction can be achieved with minimal degradation of the output spectrum. We also address EFMs with sinusoidal inputs and show how bus-splitting and error masking techniques can be used to obtain a trade-off between the modulator complexity and the achievable signal-to-noise ratio.

Design and Assessment of a 6 ps-Resolution Time-to-Digital Converter With 5 MGy Gamma-Dose Tolerance for LIDAR Application

Time-to-Digital Converters (TDCs) are key building blocks in time-based mixed-signal systems, used for the digitization of analog signals in time domain. A short survey on state-of-the-art TDCs is given. A novel multi-stage noise-shaping (MASH) delta-sigma $(\Delta\Sigma)$ TDC structure is proposed for applications in continuous-time pulsed time-of-flight (TOF) rangefinders for nuclear reactor remote sensing, which requires both high resolution and multi MGy gamma-dose radiation tolerance. The converter, implemented in 0.13 $\mu{\rm m}$ , achieves a time resolution of 5.6 ps and an ENOB of 11 bits, when the oversampling ratio (OSR) is 250. The TDC core consumes only 1.7 mW and occupies an area of 0.11 ${\rm mm}^{2}$ . Owing to the usage of circuit level radiation hardened-by-design techniques, such as passive RC oscillators and constant- $g_{m}$ biasing, the TDC exhibits enhanced radiation tolerance. At a low dose rate of 1.2 kGy/h, the frequency of the counting clock in the TDC remains constant up to at least 160 kGy. Even after a total dose of 3.4 MGy at a high dose rate of 30 kGy/h, the TDC still achieves a time resolution of 10.5 ps with an OSR of 250.

Multi stage noise shaping sigma–delta modulator (MASH) for capacitive MEMS accelerometers

Electromechanical multi stage noise shaping (MASH) sigma–delta modulator (ΣΔM) has the advantages of inherent stability, high dynamic range, and high overload input level compared with the single loop sigma–delta-modulator approach. In this paper, a fourth order electromechanical MASH is studied by Simulink modelling and hardware implementation using surface mount PCB technology. The accelerometer used in the study is fabricated using a Silicon on Insulator (SOI) wafer with a device layer thickness of 50μm, using a dicing free and dry release process. The experimental results confirm the concept of the MASH structure and show its potential as a closed loop interface concept for a high performance capacitive MEMS accelerometer. The 4th order MASH electromechanical ΣΔM system improves the performance of the 2nd order electromechanical ΣΔM by 20dB, and shows a noise floor of −110dB. Furthermore, the system is capable of handling an acceleration input of up to ±1.5g. However, the MASH-ΣΔM is sensitive to the sensor and system parameters variation; it exhibited performance degradation of 10dB, due to a leakage of the quantization noise to the input signal.

A 13 bit 10 MHz bandwidth MASH 3-2 Σ∆ modulator in 90 nm CMOS

In this paper, a new multi loop sigma-delta (ΣΔ) modulator is proposed which employs one order redundant noise shaping in the first stage so the effect of the quantization noise leakage is minimized. Thus, analog circuit requirements are considerably relaxed compared to the conventional Multi-stAge-noise-SHaping (MASH) structures. This enhancement makes the structure appropriate for low voltage and broadband applications. The proposed architecture is compared with traditional high-order structures, and the advantages are demonstrated by both the analysis and behavioral system level simulations. As a prototype, the proposed MASH 3–2 sigma-delta modulator is designed, and the detailed design procedure is presented from the system level to the circuit level in a 90 nm CMOS technology. Circuit level simulation results show that the modulator achieves a peak signal-to-noise and distortion ratio of 79.4 dB and 79 dB dynamic range over a 10 MHz bandwidth with a sampling frequency of 160 MHz. It consumes 35.4 mW power from a single 1 V supply. Copyright © 2012 John Wiley & Sons, Ltd.

A fully integrated frequency synthesizer for a dual-mode GPS and Compass receiver

This paper presents a fully integrated frequency synthesizer for a dual-mode GPS and Compass receiver fabricated in a 0.13 μm CMOS technology. The frequency synthesizer is implemented with an on-chip symmetric inductor and an on-chip loop filter. A capacitance multiplying approach is proposed in the on-chip loop filter design for area-saving consideration. Pulse-swallow topology with a multistage noise shaping ΔΣ modulator is adopted in the frequency divider design. The synthesizer generates local oscillating signals at 1571.328 MHz and 1568.259 MHz with a 16.368 MHz reference clock by working in integer and fractional modes. Measurement results show that the phase noise of the synthesizer achieves −91.3 dBc/Hz and −117 dBc/Hz out of band at 100 kHz and 1 MHz frequency offset, separately. The proposed frequency synthesizer consumes 8.6 mA from a 1.2 V power supply and occupies an area of 0.92 mm2.

A hybrid CT/DT double-sampled SMASH Σ∆ modulator for broadband applications in 90 nm CMOS technology

In this paper, a hybrid continuous-time (CT)/discrete-time (DT) multi-stage noise shaping (MASH) sigma---delta (ΣΔ) modulator architecture for broadband applications is presented. The double-sampling technique is employed in the DT second-stage modulator in order to reduce the power consumption of the overall modulator. Flat and unity signal transfer functions are used in the first- and second-stage modulators, respectively, to relax the output swing of the analog building blocks without influencing the inherent anti-aliasing behavior of the first-stage CT modulator. The proposed structure is insensitive to the amplifier limited dc gain of CT stage and avoids the need of compensation for finite gain-bandwidth induced error in CT loop filter. As a design example, the proposed MASH 2-2 modulator is designed in a 90 nm CMOS technology with 1 V power supply. Circuit level simulation results with HSPICE achieve the maximum SNDR of 74.8 dB and dynamic range of 76.5 dB in 12.5 MHz bandwidth with 17 mW power consumption while operating at 200 MHz sampling rate.

VCO based multi-stage noise shaping ADC

A way to combine several analogue-to-digital converters (ADCs) based on voltage-controlled oscillators (VCOs) to implement a multi-stage noise shaper (MASH) is proposed. By means of a simple digital circuit, the phase quantisation error in one stage is extracted as a pulsed signal. Then, this pulsed signal modulates the VCO in the next stage. First, the equations that describe the system are discussed and then a hardware implementation suitable for low power applications is proposed. The proposed implementation circuit also desensitises the ADC from the VCO nonlinearity by precoding the input signal using a pulse width modulation modulator.

A 0.13 μm CMOS ΔΣ fractional-N frequency synthesizer for WLAN transceivers

A fractional-N frequency synthesizer fabricated in a 0.13 μm CMOS technology is presented for the application of IEEE 802.11 b/g wireless local area network (WLAN) transceivers. A monolithic LC voltage controlled oscillator (VCO) is implemented with an on-chip symmetric inductor. The fractional-N frequency divider consists of a pulse swallow frequency divider and a 3rd-order multistage noise shaping (MASH) ΔΣ modulator with noise-shaped dithering techniques. Measurement results show that in all channels, phase noise of the synthesizer achieves −93 dBc/Hz and −118 dBc/Hz in band and out of band respectively with a phase-frequency detector (PFD) frequency of 20 MHz and a loop bandwidth of 100 kHz. The integrated RMS phase error is no more than 0.8°. The proposed synthesizer consumes 8.4 mW from a 1.2 V supply and occupies an area of 0.86 mm2.

Hardware Reduction in Digital Delta-Sigma Modulators Via Bus-Splitting and Error Masking—Part I: Constant Input

In this two-part paper, a design methodology for hardware reduction in digital delta-sigma modulators (DDSMs) based on bus-splitting and error masking is presented. Part I addresses Multi stAge noise SHaping (MASH) DDSMs with constant inputs; Part II focuses on error feedback modulators (EFMs) with time-varying inputs. In this paper, we address EFMs with DC inputs plus additive input least significant bit (LSB) dithering and show how hardware reduction can be achieved with minimal degradation of the output spectrum. We also address EFMs with sinusoidal inputs and show how bus-splitting and error masking techniques can be used to obtain a trade-off between the modulator complexity and the achievable signal-to-noise ratio.

A Spur-Free MASH DDSM With High-Order Filtered Dither

A novel dithered multistage noise shaping (MASH) digital delta-sigma modulator (DDSM) that produces a spur-free output spectrum is presented. The order of the least significant bit (LSB) dither shaping can be increased to that of the modulator, without producing spurious tones. Theoretical results prove that the quantization noise is asymptotically white and uncorrelated with the input; this is corroborated by behavioral simulations.

Multi Stage Noise Shaping Sigma-delta Modulator (MASH) for Capacitive MEMS Accelerometers

Electromechanical multi stage noise shaping sigma-delta modulator (MASH) has the advantages of inherent stability, high dynamic range, and high overload input level compared with the single loop sigma-delta-modulator approach. In this paper, a fourth order electromechanical MASH is studied by Simulink modeling and hardware implementation using surface mount PCB technology. The accelerometer used in the study is fabricated using a Silicon on Insulator (SOI) wafer with a device layer thickness of 50um, using a dicing free and dry release process. The experimental results confirm the concept of the MASH structure and show its potential as a closed loop interface concept for a high performance capacitive MEMS accelerometer.

LOW-VOLTAGE DOUBLE-SAMPLED HYBRID CT/DT ΣΔ MODULATOR FOR WIDEBAND APPLICATIONS

A hybrid continuous-time (CT)/discrete-time (DT) multi-stage noise-shaping (MASH) ΣΔ modulator architecture is presented. The double-sampling technique is employed in the DT second stage modulator. A flat and a unity signal transfer functions (STFs) are used in the first and second stage modulators, respectively, to make the modulator robust to nonlinearities of the analog circuitry and well suited for low-voltage applications without influencing the inherent anti-aliasing behavior of the first stage CT modulator. Unlike the conventional MASH architecture, this structure is insensitive to the amplifier limited DC gain of CT stage and avoids the need of compensation for finite gain-bandwidth induced error in CT loop filter. Behavioral simulations confirm the effectiveness of the proposed scheme over existing cascaded topologies.

Efficient Dithering in MASH Sigma-Delta Modulators for Fractional Frequency Synthesizers

The digital multistage-noise-shaping (MASH) ΣΔ modulators used in fractional frequency synthesizers are prone to spur tone generation in their output spectrum. In this paper, the state of the art on spur-tone-magnitude reduction is used to demonstrate that an M -bit MASH architecture dithered by a simple M-bit linear feedback shift register (LFSR) can be as effective as more sophisticated topologies if the dither signal is properly added. A comparison between the existent digital ΣΔ modulators used in fractional synthesizers is presented to demonstrate that the MASH architecture has the best tradeoff between complexity and quantization noise shaping, but they present spur tones. The objective of this paper was to significantly decrease the area of the circuit used to reduce the spur tone magnitude for these MASH topologies. The analysis is validated with a theoretical study of the paths where the dither signal can be added. Experimental results of a digital M -bit MASH 1-1-1 ΣΔ modulator with the proposed way to add the LFSR dither are presented to make a hardware comparison.

Spur-Free MASH Delta-Sigma Modulation

For multistage noise-shaping (MASH) delta-sigma modulation, this paper presents a new structure that is free of spurs for all input values. The proposed MASH structure cascades several first-order delta-sigma modulators (DSMs) like the traditional MASH structure but has an additional feedforward connection between two adjacent stages. The proposed MASH structure can increase the sequence length and thus reduce spurs. The reason why the proposed MASH structure has a long sequence length for the full input range is mathematically proved, and simulations are performed to verify the effect of the long sequence length. Simulation results show that the performance of the proposed MASH structure is close to that of the ideal DSM. In addition, the proposed MASH structure requires almost the same hardware cost as the traditional MASH structure.

A Methodology to Teach Advanced A/D Converters, Combining Digital Signal Processing and Microelectronics Perspectives

ADCs (analog-to-digital converters), especially Pipeline and Sigma-Delta (Σ-Δ) converters, are designed using complex architectures in order to increase their sampling rate and/or resolution. Consequently, the learning of ADC devices also encompasses complex concepts such as multistage synchronization, latency, oversampling, modulation, noise shaping, filtering, or decimation. This paper is focused on a new learning methodology, based on the simulation of the main circuit topologies used in commercial ADCs, in order to understand their working principles more thoroughly. At the same time, the ADC dynamic and static tests are obtained from the simulation results, and their characterization is obtained at an application level. In this way, the methodology combines the microelectronics perspective, at the design level, with the digital signal processing perspective. This methodology saves time in practical classes and encourages self-learning because it does not require special hardware. Moreover, it uses only software tools that are common in electronic engineering, like the OrCAD PSpice simulator, a C compiler, or a hardware description language (HDL) simulator. The methodology has been validated during two consecutive offerings of academic courses in the Telecommunication Engineering curriculum at Vigo University, Vigo, Spain, and the results obtained are discussed.

Systematic design of wideband ΔΣ modulators for WiFi/WiMAX receivers

Modern multi-standard receivers in deep-submicron technologies pose significant design challenges on the analog baseband. Moving this analog filtering to the digital domain simplifies the design, yielding a process-scalable implementation. However, analog-to-digital converter (ADC) specifications now become more stringent and must be obtained by comprehending the standard and the system. Assuming a receiver NF of 5.96 dB and SNR degradation of 0.36 dB by the ADC, the proposed dual-mode WiFi/WiMAX receiver attains an input sensitivity of ?74 dBm (20 MHz channel bandwidth). To accommodate the high dynamic range and the anti-alias rejection needed for the system, a Delta-Sigma (ΔΣ) ADC is proposed. Single-loop and Multi-Stage Noise-Shaping (MASH) architectures that achieve a SNR of 69 dB at a low oversampling ratio (OSR) of 8 for a conversion bandwidth of 40 MHz (108 Mbps, OFDM) are investigated at system level. Based on thermal noise, harmonic distortion, and power tradeoffs, a ΔΣ ADC design that meets the design specifications is presented.

Subtraction Inversion for Delta Path's Hardware Simplification in MASH Delta-Sigma Modulator

The multistage noise-shaping (MASH) delta-sigma modulator (DSM) is the key element in a fractional-N frequency synthesizer. A hardware simplification method with subtraction inversion is proposed for delta-path's design in a MASH delta-sigma modulator. The subtraction inversion method focuses on simplification of adder-subtractor unit in the delta path with inversion of subtraction signal. It achieves with less hardware cost as compared with the conventional approaches. As a result, the hardware organization is regular and easy for expanding into higher order MASH DSM design. Analytical details of the implementation way and hardware cost function with N-th order configuration are presented. Finally, simulations with hardware description language as well as synthesis data verified the proposed design method.

Comparative study of multi stage noise shaping and single loop sigma–delta modulators for MEMS accelerometers

In this paper, two 4th order electromechanical sigma-delta modulators (∑ΔM) are compared at system level: a single-loop (SD4); and a multi-stage (MASH22) architecture. The comparison was performed for two different micromachined accelerometer sensing elements: one over-damped and the other under-damped; the control system with the latter requiring an electronic phase compensator for loop stability. The investigation shows that the 4th order MASH ∑ΔM is unconditionally stable and provides better noise shaping, higher signal-to-quantizationnoise-ratio (SQNR), higher dynamic range, and a higher overload input level compared with the SD4. The only drawback of the MASH22 is its sensitivity to component and parameter tolerances, which leads to a leakage of the quantization noise to the input signal and a degradation of the performance of the modulator.

An Enhanced Dual-Path .DELTA..SIGMA. A/D Converter

This paper presents an enhanced dual-path delta-sigma analog-to-digital converter. Compared with other architectures, the enhanced architecture increases the noise shaping order without any instability problems and displays analog complexity equivalent to the multi-stage noise shaping architecture. Our delta-sigma converter is based on this new architecture. It employs not only doubly-differential structure to reduce common-mode errors in the system-level but also delayed-feed-in structure to mitigate the timing constraint of the feedback signal. Regarding the circuit implementation, the first-order enhancement of the quantization noise shaping is achieved via the use of a switched capacitor circuit technique. The circuit is incorporated into the active adder in a low-distortion structure. The supporting clock generation circuit that provides additional phases of clocks with the enhancement block is also implemented in the CMOS logic gates. A digital dynamic element matching circuit (i.e., segmented data-weighted-average circuit) is designed to reduce mismatch errors caused by the feedback DAC of modulator. A test chip, fabricated in a 0.18-μm CMOS process, provides a signal-to-noise+distortion ratio (SNDR) of 75-dB for a 1.0-MHz signal bandwidth clocked at 40-MHz. The 2nd harmonic is ―101 dB and the 3rd harmonic is ―94 dB when a ―4.5-dB 100-kHz input signal is applied.