Multistage Interconnection Networks Research Articles

Optimal all-to-all personalised exchange in a novel optical multistage interconnection network

An all-to-all personalised exchange is one of the most dense collective communication operations in parallel and distributed computing and communication applications. Each node in the network needs to send a different message to each of the other nodes. Advances in electro-optic switches have made optical communication a good networking choice that can satisfy the high channel bandwidth, low communication latency, low error rate, and gigabit transmission requirements of high performance computing and communication applications. Previously proposed optical multistage interconnection networks (MINs) require at least two passes to send a message from each node to a different node (to realise a permutation) in the network. In this paper, we propose an MIN that requires only one pass to realise a permutation. That is, the new MIN requires n 1 passes instead of 2n passes, the requirement for other optical MINs, for an all-to-all personalised exchange. The new network is optimal in terms of the number of passes that is required for an all-to-all personalised exchange.

Equivalence of buddy networks with arbitrary number of stages

Equivalence of multistage interconnection networks is an important concept because it reduces the number of networks to be studied. Equivalence among the banyan networks has been well studied. Occasionally, the study was extended to networks obtained by concatenating two banyan networks (identifying the output stage of the preceding network with the input stage of the succeeding one). Recently, equivalence among the class of networks that are obtained from banyan networks by adding extra stages has also been studied. Note that all these above-mentioned networks are in the general class of buddy networks. In this article we study equivalence of buddy networks with an arbitrary number of stages. © 2005 Wiley Periodicals, Inc. NETWORKS, Vol. 46(4), 171–176 2005This article was written when the author was visiting the Center of Mathematical Sciences, Zhejiang University, Hangzhou, Zhejiang, P.R. China.

Equivalence of buddy networks with arbitrary number of stages

Equivalence of multistage interconnection networks is an important concept because it reduces the number of networks to be studied. Equivalence among the banyan networks has been well studied. Occasionally, the study was extended to networks obtained by concatenating two banyan networks (identifying the output stage of the preceding network with the input stage of the succeeding one). Recently, equivalence among the class of networks that are obtained from banyan networks by adding extra stages has also been studied. Note that all these above-mentioned networks are in the general class of buddy networks. In this article we study equivalence of buddy networks with an arbitrary number of stages. © 2005 Wiley Periodicals, Inc. NETWORKS, Vol. 46(4), 171–176 2005

Integrated fault tolerant connections-scheduling for dilated Benes network

The 2×2 electro-optical directional coupler is a common switching element in dilated optical multistage interconnection networks (DOMINs) and can be applied to photonic switching technology. Because of the undesirable coupling within an optical switch, a portion of the energy of the input signal might be transmitted to the undesired output terminal in the switch. A switch is said to be faulty if it causes excessive crosstalk above a given threshold, and optical crosstalk is a problem commonly found in DOMINs. The problem of connections-scheduling with faulty switches in a dilated re-arrangeable photonic network, say dilated Benes network (DBN), is studied and an integrated fault tolerant DBN architecture is proposed. Based on the faulty switch information given from the fault diagnosis algorithm, the fault-free path generation algorithm and scheduling algorithm are devised to schedule a set of connections avoiding faulty switches with a polynomial time complexity in the DBN. It is desirable to keep the number of rounds as small as possible. The simulation results show that the proposed method outperforms the greedy-scheduling algorithm in terms of routing number, number of failed connections, minimum number of rounds, and connection success probability when the size of the network is large. Furthermore, the proposed methodology can be embedded in the optical switching system to achieve self-testing.

Strict nonblockingness of reduced shuffle‐exchange networks

AbstractThe shuffle‐exchange network is one of the most well‐studied multistage interconnection networks. Whether a (2n − 1)‐stage shuffle‐exchange network is rearrangeable has been a challenging conjecture for some 30 years, and only recently a proof was claimed. In this article, we use the analysis method developed for EGSN networks to show that the shuffle‐exchange network can be strictly nonblocking by deleting some inputs and outputs. © 2004 Wiley Periodicals, Inc. NETWORKS, Vol. 45(1), 4–8 2005

Reallocation of paths of ABR services in a multistage interconnection network (MIN)-type ATM switch network

In this paper, we develop algorithms for reallocating paths of available bit rate (ABR) services in an asynchronous transfer mode (ATM) switch network. ATM traffic control for fair share bandwidth allocation is usually performed under the assumption that paths of all services in a switch network are fixed. However, each connection may have multiple paths from an ingress queue to an egress queue since most ATM switch networks have the structure of the multistage interconnection network of switch elements. Therefore, paths already established for ABR connections may have to be changed to enhance throughput of the switch, if the ATM switch has the capability of adjusting paths of ABR connections while they are being served. We present three algorithms, in which throughput for ABR connections is estimated to decide whether or not paths of the connections should be changed. These algorithms are compared with an existing traffic management algorithm through simulation experiments. Results of the experiments show that the suggested algorithms give higher throughput in terms of the number of transmitted ABR cells without increasing the delay time of ABR services as well as quality of service (QoS) guaranteed services or decreasing the number of transmitted cells of QoS guaranteed services.

Work-conserving distributed schedulers for Terabit routers

Buffered multistage interconnection networks offer one of the most scalable and cost-effective approaches to building high capacity routers. Unfortunately, the performance of such systems has been difficult to predict in the presence of the extreme traffic conditions that can arise in the Internet. Recent work introduced distributed scheduling, to regulate the flow of traffic in such systems. This work demonstrated, using simulation and experimental measurements, that distributed scheduling can deliver robust performance for extreme traffic. Here, we show that distributed schedulers can be provably work-conserving for speedups of 2 or more. Two of the three schedulers we describe were inspired by previously published crossbar schedulers. The third has no direct counterpart in crossbar scheduling. In our analysis, we show that distributed schedulers based on blocking flows in small-depth acyclic flow graphs can be work-conserving, just as certain crossbar schedulers based on maximal bipartite matchings have been shown to be work-conserving. We also study the performance of practical variants of these schedulers when the speedup is less than 2, using simulation.

Compact electronically aligned broadcast-enhanced all-optical switch

All-optical switches are used for many different applications. Broadcast-enhanced switches allow connection of a single input channel to numerous output channels, thus increasing further the possible application span. A compact multichannel all-optical broadcast-enhanced switch is described. This switch setup allows electronic alignment thus requires only simple construction procedures. A special importance of the proposed switch is for multistage interconnection networks where the alignment plays a major role. The switch structure is described and experimentally demonstrated.

Testing layered interconnection networks

We present an approach for fault detection in layered interconnection networks (LINs). An LIN is a generalized multistage interconnection network commonly used in reconfigurable systems; the nets (links) are arranged in sets (referred to as layers) of different size. Switching elements (made of simple switches such as transmission-gate-like devices) are arranged in a cascade to connect pairs of layers. The switching elements of an LIN have the same number of switches, but the switching patterns may not be uniform. A comprehensive fault model for the nets and switches is assumed at physical and behavioral levels. Testing requires configuring the LIN multiple times. Using a graph approach, it is proven that the minimal set of configurations corresponds to the node disjoint path sets. The proposed approach is based on two novel results in the execution of the network flow algorithm to find node disjoint path sets, while retaining optimality in the number of configurations. These objectives are accomplished by finding a feasible flow such that the maximal degree can be iteratively decreased, while guaranteeing the existence of an appropriate circulation. Net adjacencies are also tested for possible bridge faults (shorts). To account for 100 percent fault coverage of bridge faults a postprocessing algorithm may be required; bounds on its complexity are provided. The execution complexity of the proposed approach (inclusive of test vector generation and post-processing) is O(N/sup 4/WL), where N is the total number of nets, W is the number of switches per switching element, and L is the number of layers. Extensive simulation results are provided.

Stochastic Modeling of Multistage Interconnection Networks with MOSEL

Stochastic Modeling of Multistage Interconnection Networks with MOSEL

Performance characteristics of cascaded delay‐line node architectures in single‐path interconnection networks

AbstractInternally buffered multistage interconnection network architectures have been widely used in parallel computer systems and large switching fabrics. Migration from electrical domain to optical domain has raised the necessity of developing node architectures with optical buffers. Cascaded fibre delay line architectures can be seen as possible realizations of output and shared buffering in a 2 × 2‐switching element. These approaches can be used as buffered node architecture in a Banyan like interconnect.In this paper, we investigate and compare these approaches by using simulation methods. Different performance metrics, such as normalized throughput, average packet delay, packet loss rate and buffer utilization have been used under uniform and non‐uniform traffic models. Results show that the TC‐chain node Banyan network offer an improved normalized throughput and average packet delay performances under both traffic models without disrupting first‐in‐first‐out order of arrivals. The switched delay‐line requires fewer switching elements than TC and TTC architectures but at the cost of high packet delay. Copyright © 2004 John Wiley & Sons, Ltd.

Simulated annealing routing and wavelength lower bound estimation on wavelength-division multiplexing optical multistage networks

Multistage interconnection networks (MINs) are popular in switching and communication applications and have been used in tele- communication and parallel computing systems for many years. Crosstalk a major problem introduced by an optical MIN, is caused by coupling two signals within a switching element. We focus on an efficient solution to avoiding crosstalk by routing traffic through anN3N optical network to avoid coupling two signals within each switching element us- ing wavelength-division multiplexing (WDM) and a time-division ap- proach. Under the constraint of avoiding crosstalk, the interest is on realizing a permutation that uses the minimum number of passes for routing. This routing problem is an NP-hard problem. Many heuristic al- gorithms are already designed by researchers to perform this routing such as a sequential algorithm, a degree-descending algorithm, etc. The genetic algorithm is used successfully to improve the performance over the heuristic algorithms. The drawback of the genetic algorithm is its long running times. We use the simulated annealing algorithm to improve the performance of solving the problem and optimizing the result. In addition, a wavelength lower bound estimate on the minimum number of passes required is calculated and compared to the results obtained using heu- ristic, genetic, and simulated annealing algorithms. Many cases are tested and the results are compared to the results of other algorithms to show the advantages of simulated annealing algorithm. © 2004 Society of

Multistage Network With Globally Controlled Switching Stages and Its Implementation Using Optical Multi-Interconnection Modules

Plane-to-plane guided-wave-based interconnection modules are proposed as building blocks for scalable optoelectronic multistage interconnection networks (MINs). This approach leads naturally to a MIN paradigm based not on cascading switching stages containing several size-reduced crossbars, as in the shuffle-exchange (SE) networks, but on cascading permutation-reduced crossbars instead, one per stage. The interest of such an architecture lies in the control simplicity and scalability potential. Transparent circuit switching for permutation routing is possible in such an unbuffered globally switched multistage interconnection network (GSMIN). Preliminary experiments using fiber-based interconnection modules are presented. Performance analysis and simulation of a buffered GSMIN is also studied for packet routing purposes.

Efficient algorithms for checking the equivalence of multistage interconnection networks

In this paper we study the topological equivalence problem of multistage interconnection networks (MINs). We prove a new characterization of topologically equivalent MINs by means of a novel approach. Applying this characterization to log N stage MINs we completely describe the equivalence class which the Reverse Baseline belongs to. Most important, we apply the characterization to (2 log N - 1) stage MINs obtained as concatenation of two log N stage Reverse Baseline equivalent MINs: in this way, we deduce an O(N log N) time algorithm testing the equivalence of two such MINs. This result substantially improves the time complexity of the previously known algorithms (O(N4 log N)). Finally, we determine the number of different equivalence classes of (2 log N - 1) stage MINs and we characterize each of them.

Switch fabric architecture analysis for a scalable bi-directionally reconfigurable IP router

This paper provides an in-depth analysis using six basic router functional requirements, a primary switch fabrics (SFs) selection criterion, and a semi-quantitative compliance scoring scheme for 10 SFs. The goal is to select candidates that can serve a hardware (HW)-wise scalable and bi-directionally reconfigurable Internet Protocol (IP) router. HW scalability and bi-directional HW reconfigurability for an IP router denote respectively its ability to (1) expand according to network traffic capacity growth; and (2) be functionally converted to perform in two conceptual directions on-demand: downward as edge, or upward as hub or backbone router according to the layer of the internet services provider's network hierarchy it is targeted to serve at the moment. Overall result points to Hypercube, Multistage Interconnection Network (MIN), and 3-Dimensional Torus Mesh as potential candidates.

Modeling and analysis of fault tolerant multistage interconnection networks

Performance and reliability are two of the most crucial issues in today's high-performance instrumentation and measurement systems. High speed and compact density multistage interconnection networks (MINs) are widely-used subsystems in different applications. New performance models are proposed to evaluate a novel fault tolerant MIN arrangement, thereby assuring performance and reliability with high confidence level. A concurrent fault detection and recovery scheme for MINs is considered by rerouting over redundant interconnection links under stringent real-time constraints for digital instrumentation such as sensor networks. A switch architecture for concurrent testing and diagnosis is proposed. New performance models are developed and used to evaluate the compound effect of fault tolerant operation (inclusive of testing, diagnosis, and recovery) on the overall throughput and delay. Results are shown for single transient and permanent stuck-at faults on links and storage units in the switching elements. It is shown that performance degradation due to fault tolerance is graceful while performance degradation without fault recovery is unacceptable.

A survey of noriblocking multicast three-stage clos networks

The author gave a survey on multicast nonblocking multistage interconnection networks in his 1998 book. Here he focuses on the three-stage Clos network and its recursive extensions. Not only does this article bring the literature up to date, but it also provides some fresh viewpoints to either clarify or simplify some issues.

Multistage interconnection networks for parallel viterbi decoders

We propose new multistage interconnection networks (MIN) for scalable parallel Viterbi decoder architectures. The architecture consists of the desired number of processing elements (PE) connected by the suggested MINs, thus allowing a tradeoff between complexity and speed. The structure of the MIN is derived first by transforming the de Bruijn interconnection-based Viterbi algorithm trellis into the equivalent trellis with a perfect shuffle interconnection, and then applying a new decomposition of the perfect shuffle operator. This results in an efficient modular system and data flow is formed by the shuffling in a local PE memory and data exchange through a fixed interconnection between PEs. We suggest several solutions for 1/n and k/n rate codes, where k denotes the number of input bits shifting into k shift registers of the encoder and, at each cycle, the encoder produces n output bits as linear combinations of certain bits in the shift registers.

Nonuniform memory reference of multistage interconnection networks

A multistage interconnection network (MIN) can be used to connect the processors and memory modules in a tightly coupled multiprocessor system. Previous analyses of bandwidth for MINs are restricted to several specified memory reference models: uniform, favorite and hotspot. In the paper, analysis for MIN bandwidth under general (nonuniform) memory reference model is presented.

다단계 상호 연결망 기반의 다중 스위치 구조를 갖는 입력 버퍼형 이중 반얀 스위치

ATM망에서 사용하기 위해 다양한 형태의 스위치 구조가 제안되어 왔으며, 다단계 상호 연결망은 오늘날 망연동시 널리 사용되는 ATM 교환시스템을 구성하는 중요한 요소이다. 이러한 상호 연결망에서 가장 잘 알려진 형태중의 하나가 반얀망이다. 반얀망은 라우팅 체계의 단순함과 하드웨어 복잡도가 단순하다는 점 때문에 많이 사용되어 왔으나, 처리 효율이 내부 블록킹과 출력에서의 혼잡도에 의해 크게 제한되는 단점이 있다. 본 논문에서는 스위치 내에서의 이러한 내부 블록킹 및 HOL 블록킹을 피하기 위해 다중 스위칭 패브릭 구조를 사용하는 입력 버퍼형 이중 반얀 스위치 모델을 제안한다. 성능 분석과 시뮬레이션을 통해서 제안한 본 모델이 기존 다른 반얀 스위치 구조에 비해 우수한 96%의 처리율과 낮은 셀 지연을 가지고 있음을 보여준다. Many types of switching fabrics have been proposed for use in ATM networks. Multistage Interconnection Networks (MINs) constitute a large class of ATM switching systems that are widely used in today´s internetworking. One of the most veil-known types of multistage networks is the banyan network. The banyan network is attractive for its simple routing scheme and low hardware complexity, but its throughput is very limited due to internal blocking and output contention. In this paper, we propose an input-buffered dual-banyan switch model with multiple switching fabric between switch input and output to avoid internal and Head-of Line blocking. By performance analysis and simulation, we show that our model has a lower ceil delay and 96% throughput which is much better than other banyan-type switch architecture.