Multiprocessor System-on-chip Design Research Articles

MPSoC design and implementation using microblaze soft core processor architecture for faster execution of arithmetic application

The research paper presents the design methodology with novel task distribution technique on multi-processor system on chip (MPSoC) for speeding up the execution of arithmetic application. Utilisation of multiple soft core processors on field programmable gate array (FPGA) reduces the overload of adding external hardware to a system. Parallel processing of soft core processor with proposed task distribution technique makes any application to execute at faster rate. This task distribution based speed enhancement technique for arithmetic application is very feasible and appealing to the modern applications like neural networks, fuzzy logic, algorithms of machine learning etc. Experimentation on such architecture with arithmetic application shows significant increase in speed of operation with respect to conventional design. This is implemented using Microblaze soft core processor architecture on Xilinx Virtex 5 FPGA board.

MeXT-SE: A Design Tool to Transparently Generate Secure MPSoC

Hardware accelerators are increasingly employed in conjunction with general-purpose processors to meet stringent performance constraints. In these heterogeneous systems, security has become a prime concern. In this article, we present a design approach to generate platform-independent secure multiprocessor systems-on-chip (MPSoC) from a high-level abstraction. The aim of this article is to simplify the implementation of MPSoC, while ensuring security. The proposed design flow starts with a set of abstract and concrete specifications of a system, provided by the user, and ends up generating a generic description of the appropriate hardware design by setting up the communication structure of different components. The resulting abstract architecture is further processed using the vendor tool-chain to generate the target platform’s configuration. To enforce security, we proposed a distributed isolation framework for multilevel security, resource assess control including access to and from hardware accelerators. From a user specification, the security layer is transparently generated and security rules and requirements transparently enforced at run-time. Experimentation results show that our proposed tool can generate MPSoC designs capable of providing secure hardware execution with negligible execution overhead.

Latency Minimization using Mesochronous Scheduling in MPSoC Operation

High speed computing is the upcoming challenge for next generation applications. To cope with high speed operations, new processing architectures are evolving. Multi processor design is one optimal design approach for such need. In the design development of multi processor unit, Multi-Processor System-on-Chip (MPSoC) has an outcome in the domain of VLSI design. MPSoC are designed to process multiple instructions and data handling simultaneously. The parallel processing feature make this unit faster and optimal design for upcoming applications. However, MPSoC operations have a latency issue in clock allocation and resource utilization, which effects the processing efficiency and introduces delay and resource overhead in MPSoC interface. This paper outlines a Mesochronous operation in MPSoC design for minimizing latency in clock allocation and resource allocation, hence improving the speed of operation.

High Speed Cycle-Approximate Simulation of Embedded Cache-Incoherent and Coherent Chip-Multiprocessors

The increasing density of silicon processes, coupled with the development of ever more energy and space efficient embedded core designs, has led to multi-processor system-on-chip (MPSoC) designs becoming increasingly attractive for use in embedded systems. Unfortunately this increase in core count gives rise to an explosion in design space possibilities, especially when heterogeneous designs are considered. To address this problem, new techniques in simulation are required to increase the simulation performance of these systems, while maintaining the accuracy needed to make good design decisions, and to verify the performance characteristics for real-time systems. We present a new high-speed, near cycle-accurate simulator, addressing an important but neglected category of multicore systems: deeply-embedded cache-incoherent MPSoCs. We take advantage of the unique properties of these systems to relax synchronisation constraints and increase the parallelism of the simulation. In doing so we achieve performance not possible using previous simulation techniques, without compromising the accuracy of the results. Quantitative performance results are presented across a large range of simulated MPSoC designs, comprising 1–64 cores, on average we simulate at 5.7 MIPS, with simulation speeds reaching 377 MIPS in the best case. Comparing against FPGA implementations we demonstrate that the simulator manages this with an average timing error of only 2.1%. Applying some of these techniques to coherent simulation enables even coherent 64-core designs to be simulated accurately at up to 2.2 MIPS.

Multi-level energy/power-aware design methodology for MPSoC

Multiprocessor Systems-on-Chip (MPSoC) are becoming one of the most used solutions in order to meet the growing computation requirements of modern embedded applications. In such systems, power/energy consumption is a critical metric that should be taken into account in the design flow. System designers need an efficient power-aware design methodology and tools to cope with the complexity of MPSoC design. To address this challenge, we present in this paper a power-aware design methodology that relies on multi-level design space exploration. We propose a two-phase exploration process making profit first from functional-level simulations to reduce rapidly and significantly the solution space, and second from transactional-level simulations for better accuracy to select the most appropriate solution. Our methodology uses the same power modeling approach for the MPSoC at both the functional and transactional levels in order to guarantee the coherence of the estimation strategy. Furthermore, our methodology integrates runtime optimization techniques to reduce the energy/power consumption of the system. The efficiency of the proposed power-aware design methodology was demonstrated through a H.264 video decoder case study.

Design of NIOS II Soft-Core based Partial Reconfiguration Controller in FPGA for MPSoC Design

Recent advancement and research in FPGA has led to the development of energy optimization techniques and runtime partial reconfiguration in FPGA. This work describes an effective approach for power reduction techniques in FPGA based Multiprocessor system-on-Chip (MPSoC) platform and it works on partial reconfiguration technique during runtime. Partial reconfiguration is implemented to reconfigure only a part of FPGA dynamically and other parts of the device continues there operation undisturbed. NIOS II soft-core processor is programmed as control processor to perform reconfiguration partially and also it manages the dynamic power optimization process. This control process is further configured for clockgating which works on a FPGA logic element and cut down a substantial part of dynamic power dissolution in FPGA. Proposed power optimized low power MPSoC is implemented using ALTERA cyclone III FPGA and its power analysis is performed and summarized.

Safe Dynamic Reshaping of Reconfigurable MPSoC Embedded Systems for Self-Healing and Self-Adaption Purposes

Multiprocessor system-on-chip (MPSoC) architectures are a huge challenge in embedded system design. This situation arises from the fact that available MPSoCs and related designs flows are not tailored to the specific needs of embedded systems. This work demonstrates how to provide self-healing properties in embedded MPSoC design. This is achieved by combining the features of a generic approach to create virtualizable MPSoCs out of off-the-shelf embedded processors with a methodology to derive system configurations, such as task-processor bindings, which are optimal in terms of safety and execution time. The virtualization properties enable a reshaping of the MPSoC at runtime. Thus, system configurations may be exchanged rapidly in a dynamic fashion. As a main result of this work, embedded multiprocessor systems are introduced, which dynamically adapt to changing operating conditions, possible module defects, and internal state changes. We demonstrate the figures of merit of such reconfigurable MPSoC embedded systems by means of a complex automotive application scenario mapped to an FPGA featuring a virtualizable array of eight soft-core processors.

Deterministic reversible MPSoC debugger based on virtual platform execution traces

The increasing complexity of multiprocessor system on chip (MPSoC) makes the software developers life harder when chasing bugs. The debugging process is particularly tedious as it involves analyzing parallel execution flows. Executing a program many times is an integral part of the process in conventional debugging, but the non-determinism due to parallel execution often leads to different execution paths and different behaviors. In this paper, we propose an approach based on simulation, as it is nowadays an integral part of the MPSoC design flow, to ease pin-pointing bugs in a parallel execution. To that aim, we collect traces using a virtual platform, and when an execution fails, re-execute the traces, in either forward or reverse direction. We define a trace model suitable for this task, and detail a strategy for providing forward and reverse execution features to avoid long simulation times during a debug session. We demonstrate experimentally that re-execution is a deterministic process which, when debugging using the usual trial and error developer approach, is much faster than simulation.

Shielding Heterogeneous MPSoCs From Untrustworthy 3PIPs Through Security- Driven Task Scheduling

Multiprocessor system-on-chip (MPSoC) platforms face some of the most demanding security concerns, as they process, store, and communicate sensitive information using third-party intellectual property (3PIP) cores. The complexity of MPSoC makes it expensive and time consuming to fully analyze and test during the design stage. This has given rise to the trend of outsourcing design and fabrication of 3PIP components, that may not be trustworthy. To protect MPSoCs against malicious modifications, we impose a set of security-driven diversity constraints into the task scheduling step of the MPSoC design process, enabling the system to detect the presence of malicious modifications or to mute their effects during application execution. We pose the security-constrained MPSoC task scheduling as a multidimensional optimization problem, and propose a set of heuristics to ensure that the introduced security constraints can be fulfilled with a minimum impact on the other design goals such as performance and hardware. Experimental results show that without any extra cores, security constraints can be fulfilled within four vendors and 81% overhead in schedule length.

The Status and Challenges of Multi-Processor System-on-Chip’s Formal Verification

With the continuous advancement of processor manufacturing process as well as the exposed limitations of single-core Processors, Multi-Processor System-on-Chip (MPSoC) has become the inevitable outcome of the technological development and practical application needs. It is used to meet the requirements of multitasking, multifunctional and high performance computing. With the improvement of chip complexity, verification module also increases exponentially. Verification of MPSoC is becoming Bottleneck in the process of chip’s design. So this paper first introduces the origin of MPSoC, and analyzes developing tendency of its verification. And then, the theory and main challenges to the formal verification of MPSoC are discussed. This paper will provide support for building the verified theory method and technology that can meet the demand of MPSoC design, and Developing MPSoC high-level architecture design verification technology.

MVx-modeling: A Modeling Environment for Embedded Software Design of Heterogeneous MPSoC

Owing to the complexity and flexibility in heterogeneous multiprocessor System-on-Chip (MPSoC) architecture, parallel programming has become a tough and urgent problem to solve. Model-based development methodology improves the software production efficiency and the reliability. Some model development tools such as Simulink and Rhapsody are widely applied in the development of embedded applications. But they do not satisfy the characteristics of embedded heterogeneous multi-core software. Thus developing a general modeling environment for model-based software design is necessary and meaningful. This paper designed and implemented a graphical modeling platform MVx-modeling by using the object-oriented programming technology and Visual C#.NET development language. Practical application shows MVx-modeling platform easy-to-use and efficient. It speeds embedded application development and lowers software costs for heterogeneous MPSoC. DOI : http://dx.doi.org/10.11591/telkomnika.v12i3.4468 Full Text: PDF

Effective Task Scheduling and IP Mapping Algorithm for Heterogeneous NoC-Based MPSoC

Quality of task scheduling is critical to define the network communication efficiency and the performance of the entire NoC- (Network-on-Chip-) based MPSoC (multiprocessor System-on-Chip). In this paper, the NoC-based MPSoC design process is favorably divided into two steps, that is, scheduling subtasks to processing elements (PEs) of appropriate type and quantity and then mapping these PEs onto the switching nodes of NoC topology. When the task model is improved so that it reflects better the real intertask relations, optimized particle swarm optimization (PSO) is utilized to achieve the first step with expected less task running and transfer cost as well as the least task execution time. By referring to the topology of NoC and the resultant communication diagram of the first step, the second step is done with the minimal expected network transmission delay as well as less resource consumption and even power consumption. The comparative experiments have shown the preferable resource and power consumption of the algorithm when it is actually adopted in a system design.

On-Chip Sensor Network for Efficient Management of Power Gating-Induced Power/Ground Noise in Multiprocessor System on Chip

Reducing feature sizes and power supply voltage allows integrating more processing units (PUs) on multiprocessor system on chip (MPSoC) to satisfy the increasing demands of applications. However, it also makes MPSoC more susceptible to various reliability threats, such as high temperature and power/ground (P/G) noise. As the scale and complexity of MPSoC continuously increase, monitoring and mitigating reliability threats at runtime could offer better performance, scalability, and flexibility for MPSoC designs. In this paper, we propose a systematic approach, on-chip sensor network (SENoC), to collaboratively predict, detect, report, and alleviate runtime threats in MPSoC. SENoC not only detects reliability threats and shares related information among PUs, but also plans and coordinates the reactions of related PUs in MPSoC. SENoC is used to alleviate the impacts of simultaneous switching noise in MPSoC's P/G network during power gating. Based on the detailed noise behaviors under different scenarios derived by our circuit-level MPSoC P/G noise simulation and analysis platform, simulation results show that SENoC helps to achieve on average 26.2 percent performance improvement compared with the traditional stop-go method with 1.4 percent area overhead in an 8*8-core MPSoC in 45 nm. An architecture-level cycle-accurate simulator based on SystemC is implemented to study the performance of the proposed SENoC. By applying sophisticated scheduling techniques to optimize the total system performance, a higher performance improvement of 43.5 percent is achieved for a set of real-life applications.

Silicon-aware distributed switch architecture for on-chip networks

It is well-known that current Chip MultiProcessor (CMP) and high-end MultiProcessor System-on-Chip (MPSoC) designs are growing in their number of components. Networks-on-Chip (NoC) provide the required connectivity for such CMP and MPSoC designs at reasonable costs. As technology advances, links become the critical component in the NoC due to their long delay and power consumption, becoming unacceptable for long global interconnects. In this paper we present a new switch architecture that reduces the negative impact of links on the NoC. We call our proposal distributed switch. The distributed switch spreads the circuitry of the switch onto the links. Thus, packets are buffered, routed, and forwarded at the same time they are crossing the link. Distributing a modular switch onto the link improves the trade off between the power consumption and the operating frequency of the entire network. On the contrary, area resources are increased. Additionally, the distributed switch presents better fault tolerance and process variation behavior with respect to a non-distributed switch.

Automatic Generation of Transducer Models for Bus-Based MPSoC Design

This paper presents methods for automatic generation of models of Transducer, a highly flexible communication module for interfacing Multiprocessor System-on-Chip (MPSoC) components. We describe the transducer architecture, comprising the bus interface, high-level communication controllers and buffer management blocks. The well-defined architecture of the transducer enables automatic generation of its Transaction-level and Register-transfer level (RTL) models. Moreover, the simple interface of the transducer provides for a well-defined software interface, making it easy to update the software after changes in MPSoC platform. Our experimental results show that MPSoC design for industrial-size applications, such as MP3 decoder and JPEG encoder, greatly benefits from automatic generation of transducer models. We found productivity gains of 9-23× due to significant savings in modeling effort. On the quality axis, we show that MPSoC communication design using automatically generated transducers has very little overhead in communication delay over a fully connected point-to-point communication architecture. Finally, we show that our automatically generated TLMs greatly reduce the system-level modeling time and provide a fast executable model for early functional validation.

Embedding formal performance analysis into the design cycle of MPSoCs for real-time streaming applications

Modern real-time streaming applications are increasingly implemented on multiprocessor systems-on-chip (MPSoC). The implementation, as well as the verification of real-time applications executing on MPSoCs, are difficult tasks, however. A major challenge is the performance analysis of MPSoCs, which is required for early design space exploration and final system verification. Simulation-based methods are not well-suited for this purpose, due to long runtimes and non-exhaustive corner-case coverage. To overcome these limitations, formal performance analysis methods that provide guarantees for meeting real-time constraints have been developed. Embedding formal performance analysis into the MPSoC design cycle requires the generation of a faithful analysis model and its calibration with the system-specific parameters. In this article, a design flow that automates these steps is presented. In particular, we integrate modular performance analysis (MPA) into the distributed operation layer (DOL) MPSoC programming environment. The result is an MPSoC software design flow that allows for automatically generating the system implementation, together with an analysis model for system verification.

Prototype Design and Synthesis of Cluster MPSoC Architecture for Multiple Applications

Modern embedded devices require high performances such as computing, throughput and power consumption. Multiprocessor System-on-Chip (MPSoC) is a promising solution to meet the requirements. And the Network-on-Chip (NoC) is used as the interconnection of MPSoC. Whereas it brings more challenge on application programming and fast design exploration of software and hardware implements automatically. In this paper we propose a cluster MPSoC architecture, which adopts hybrid interconnection of processor clusters and NoC. And we present a design automation and synthesis methodology to generate MPSoCs in a system-level way for multiple application use-cases. And it merges them onto a minimal hardware architecture of resources. The desired MPSoC design is generated with short design time, making it suited for fast design exploration for MPSoC development. The proposed design flow is implemented into a tool for Xilinx FPGAs. The experiments results illuminate that our design methodology is a convenient approach to generate the MPSoC design for multiple use-cases.

Parallel application sampling for accelerating MPSoC simulation

Multi-processor system-on-chip (MPSoC) simulators are many orders of magnitude slower than the hardware they simulate due to increasing architectural complexity. In this paper, we propose a new application sampling technique to accelerate the simulation of MPSoC design space exploration (DSE). The proposed technique dynamically combines simultaneously executed phases, thus generating a sampling unit. This technique accelerates the simulation by allowing the repeated combinations of parallel phases to be skipped. A complementary technique, called cluster synthesis, is also proposed to improve the simulation acceleration when the number of possible phase combinations increases. Our experimental results show that this technique can accelerate the simulation up to a factor of 800 with a relatively small estimation error.

Proportionally fair flow control mechanism for best effort traffic in network-on-chip architectures

The research community has recently witnessed the emergence of multi-processor system on chip (MPSoC) platforms consisting of a large set of embedded processors. Particularly, Interconnect networks methodology based on network-on-chip (NoC) in MPSoC design is imminent to achieve high performance potential. More importantly, many well established schemes of networking and distributed systems inspire NoC design methodologies. Employing end-to-end congestion control is becoming more imminent in the design process of NoCs. This paper presents a centralised congestion control scheme in the presence of both elastic and streaming flow traffic mixture. We model the desired best effort source rates as the solution to an optimisation problem with weighted logarithmic objective which is known to admit proportional fairness criterion. The problem is constrained with link capacities while preserving guaranteed service traffics services requirements at the desired level. We propose an iterative algorithm as the solution to the optimisation problem which has the benefit of low complexity and fast convergence, and can be implemented by a controller unit with low computation and communication overhead.

Design exploration and automatic generation of MPSoC platform TLMs from Kahn Process Network applications

With increasingly more complex Multi-Processor Systems on Chip (MPSoC) and shortening time-to-market projections, Transaction Level Modeling and Platform Aware Design are seen as promising >approaches to efficient MPSoC design. In this paper, we present an automatized 3-phase process of Platform Aware Design and apply it to Kahn Process Networks (KPN) applications, a widely used model of computation for data-flow applications. We start with the KPN application and an abstract platform template and automatically generate an executable TLM with estimated timing that accurately reflects the system platform. We support homogeneous and heterogeneous multi-master platform models with shared memory or direct communication paradigm. The communication in heterogeneous platform modules is enabled with the transducer unit (TX) for protocol translation. TX units also act as message routers to support Network on Chip (NoC) communication. We evaluate our approach with the case study of the H.264 Encoder design process, in which the specification compliant design was reached from the KPN application in less than 2 hours. The example demonstrates that automatic generation of platform aware TLMs enables a fast, efficient and error resilient design process.