Multiprocessor Shared Memory Systems Research Articles

The Tiny-Tasks Granularity Trade-Off: Balancing Overhead Versus Performance in Parallel Systems

Models of parallel processing systems typically assume that one has <inline-formula><tex-math notation="LaTeX">$l$</tex-math></inline-formula> workers and jobs are split into an equal number of <inline-formula><tex-math notation="LaTeX">$k=l$</tex-math></inline-formula> tasks. Splitting jobs into <inline-formula><tex-math notation="LaTeX">$k &gt; l$</tex-math></inline-formula> smaller tasks, i.e. using “tiny tasks”, can yield performance and stability improvements because it reduces the variance in the amount of work assigned to each worker, but as <inline-formula><tex-math notation="LaTeX">$k$</tex-math></inline-formula> increases, the overhead involved in scheduling and managing the tasks begins to overtake the performance benefit. We perform extensive experiments on the effects of task granularity on an Apache Spark cluster, and based on these, develop a four-parameter model for task and job overhead that, in simulation, produces sojourn time distributions that match those of the real system. We also present analytical results which illustrate how using tiny tasks improves the stability region of split-merge systems, and analytical bounds on the sojourn and waiting time distributions of both split-merge and single-queue fork-join systems with tiny tasks. Finally we combine the overhead model with the analytical models to produce an analytical approximation to the sojourn and waiting time distributions of systems with tiny tasks which include overhead. We also perform analogous tiny-tasks experiments on a hybrid multi-processor shared memory system based on MPI and OpenMP which has no load-balancing between nodes. Though no longer strict analytical bounds, our analytical approximations with overhead match both the Spark and MPI/OpenMP experimental results very well.

COOL MULTITHREADING IN HTMT SPELL-1 PROCESSORS

A COOL-1 multiprocessor shared memory system based on superconductor Rapid Single-Flux Quantum (RSFQ) technology is being developed at SUNY (Stony Brook, USA) within the framework of the Hybrid Technology Multithreaded architecture (HTMT) petaflops project led by JPL. This paper describes a multithreading approach proposed in the COOL-I architecture and mechanisms to exploit the thread level parallelism in RSFQ processors called SPELL-1. Up to 128 fine-grain threads called (instruction) streams arranged in 16 groups of 8 streams each can run in parallel within a SPELL-1 processor. All eight streams comprising each COOL stream cluster can communicate and synchronize directly via shared registers. Fast creation and termination of streams including speculative stream execution are also supported.

COOL Multithreading in HTMT SPELL-1 Processors

A COOL-1 multiprocessor shared memory system based on superconductor Rapid Single-Flux Quantum (RSFQ) technology is being developed at SUNY (Stony Brook, USA) within the framework of the Hybrid Technology Multithreaded architecture (HTMT) petaflops project led by JPL. This paper describes a multithreading approach proposed in the COOL-I architecture and mechanisms to exploit the thread level parallelism in RSFQ processors called SPELL-1. Up to 128 fine-grain threads called (instruction) streams arranged in 16 groups of 8 streams each can run in parallel within a SPELL-1 processor. All eight streams comprising each COOL stream cluster can communicate and synchronize directly via shared registers. Fast creation and termination of streams including speculative stream execution are also supported.

Lazy caching

This paper examines cache consistency conditions for multiprocessor shared memory systems. It states and motivates a weaker condition than is normally implemented. An algorithm is presented that exploits the weaker condition to achieve greater concurrency. The algorithm is shown to satisfy the weak consistency condition. Other properties of the algorithm and possible extensions are discussed.

A Model for Memory Interference in Multiprocessors

Am odel is described and analyzed for a multiprocessor shared memory system in which each memory bank can service a fixed number of access requests per cpu cycle. If n processors simultaneously request data from a common shared memory, it is usually not possible for all the requests to be satisfied at the same time. This is because the memory system usually places a limit on the number of requests that it can service at any given time. A typical method for allowing multiple requests to be satisfied is to divide the memory into m banks each capable of satisfying requests independently. The memory banks are usually interleaved, so that requests to successive memory locations will be serviced by successive memory banks. Even if m = n, full memory bus bandwidth cannot usually be achieved. This is because of the fact that if n processors each make a memory request at random, it is unlikely that the n requests will all be to different memory banks. In fact, the probability that the n requests go to all n banks is just the number of permutations of Zn divided by the number of mappings of Zn into Zn, where Zn represents the set of integers from 1 to n. This probability is n! n n which, as n gets large, approaches √ 2πn/e n by Stirling's Formula. One solution is to make m>n . Since the cost increases with the number of memory banks, it is important to know how the average memory bandwidth will be affected by the values of m and n. Several mathematical models have appeared in the literature to predict the behavior of such systems (1-5,8,11-13). The model that is closest to the behavior of the machine we are interested in (the Alliant FX/8 multiprocessor) is the model that Hoogendoorn (8) calls the Uniform Static-Access Matrix. In this model, each processor accesses each memory bank with equal probability (1/m). The memory requests are considered to be random and independent. If a memory bank gets more than one request, it services precisely one of the requests. The other requests are rejected and are not queued up. There is no assumption that the requesting processor will make the same request on the next cpu cycle. (This is clearly a deficiency in this model.) Ravi (13) showed that the expected number of requests that are serviced is