Multi-phase Clock Research Articles

A 0.55-mm2 8-bit 32-GS/s TI-SAR ADC with optimized hierarchical sampling architecture

This paper analyzes the bandwidth of the time-interleaved analog-to-digital converter (TI-ADC) with hierarchical sampling and presents an 8-bit 32-GS/s TI-ADC in 28-nm CMOS. The front-end sampler is implemented by a two-stage hierarchical sampling architecture to extend the analog input bandwidth. The 32-way sub-ADCs are realized with 2b/cycle successive approximation register (SAR) architecture and non-binary search strategy, which meet the requirements of high speed, medium resolution, and strong robustness. Multi-phase low-jitter clock tree is designed based on the delay-locked loop (DLL). Calibration methods for timing skew, offset and gain mismatches are introduced to improve accuracy. The proposed TI-SAR ADC achieves an analog input bandwidth of 23.7 GHz. It occupies an active area of 0.55 mm2 and consumes 356 mW at 1.8/1 V supply.

A 12-bit, 27.8-ps resolution, Anti-PVT variation multi-parallel sampling based coarse-fine TDC for LiDAR sensors

This paper presents a multi-parallel sampling based coarse-fine time-to-digital converter (TDC) with sub-gate delay resolution, large measurement range and high conversion rate for light detection and ranging (LiDAR) sensors. The fine-TDC is designed based on a voltage-controlled delay line (VCDL) but with multi-parallel sampling D flip-flop (DFF) groups to achieve a sub-gate delay resolution based on multi-phase interpolation. These DFF groups are triggered by several successively delayed sampling clocks that generated by a phase-locked loop (PLL) based multi-phase clock generator. The coarse-TDC composed of a coarse counter and a logical control circuit (LCC) is designed to enlarge the measurement range. The LCC is used to calibrate and guarantee the coarse counter neither over-counted nor under-counted. Since the delay of delay units in fine-TDC is also voltage-controlled by another PLL, the resolution of this proposed TDC is robust to process-voltage-temperature (PVT) variation. Besides, this proposed TDC architecture also has the property of dynamic element matching (DEM), which contributes to mitigate the impact of device mismatch and scramble the quantization noise. The post-layout simulations demonstrate a 12-bit, 27.8-ps time resolution, 0.86-LSB DNL, 0.92-LSB INL with 13.6-mW power consumption at 33.3-MS/s under a 1.8-V supply.

Underwater Single-Photon Lidar Equipped with High-Sampling-Rate Multi-Channel Data Acquisition System

Lidar has emerged as an important technology for the high-precision three-dimensional remote sensing of the ocean. While oceanic lidar has been widely deployed on various platforms, its underwater deployment is relatively limited, despite its significance in deep-sea exploration and obstacle avoidance for underwater platforms. Underwater lidar systems must meet stringent requirements for high performance, miniaturization, and high integration. Single-photon lidar, by elevating the detection sensitivity to the single-photon level, enables high-performance detection under the condition of a low-pulse-energy laser and a small-aperture telescope, making it a stronger candidate for underwater lidar applications. However, this imposes demanding requirements for the data acquisition system utilized in single-photon lidar systems. In this work, a self-developed multi-channel acquisition system (MCAS) with a high-resolution and real-time histogram statistics capability was developed. By utilizing field-programmable gate array (FPGA) technology, a method that combines coarse counters with multi-phase clock interpolation achieved an impressive resolution of 0.5 ns and enabled a time of flight duration of 1.5 μs. To address counting instability, a dual-counter structure was adopted in the coarse counter, and real-time histogram statistics were achieved in the data acquisition system through a state machine. Furthermore, the non-uniform phase shift of the clock was analyzed, and a correction algorithm based on code density statistics was proposed to mitigate the periodic modulation of the backscattered signal, with the effectiveness of the algorithm demonstrated through experimental results. The robustness and stability of the MCAS were validated through an underwater experiment. Ultimately, the development of this compact acquisition system enables the implementation of underwater single-photon lidar systems, which will play a crucial role in underwater target imaging, obstacle avoidance in underwater platforms, and deep-sea marine environment monitoring.

A Wideband 4-Phase Phase-Locked Loop for Single-Slope Ramp ADC in SCA ASIC

Waveform digitization is an important research direction in high-energy physics experiments. Compared to analog-to-digital converter (ADC) solutions, switched capacitor arrays (SCAs) have the advantages of high sampling rate, low power consumption, and easy multichannel integration. However, the dead time of SCA is a limitation for high-hit-rate applications. To reduce the quantization time contributed by the on-chip Wilkinson ADC, a strategy of a high-speed less-bit coarse counter combined with multi-phase clock locking can be adopted. In this case, a high-precision PLL with multiple phases is needed. This paper presents the design and test of a 4-phase PLL for a 12-bit single-slope ramp ADC employed in our SCA ASIC in research. It contains a linear phase and frequency detector (PFD), a current steering charge pump (CP), a second order loop filter, a wideband voltage-controlled oscillator (VCO), VCO calibration, a band-locked detector, and a frequency divider (FD). The frequency tuning range is achieved from 1 GHz to 2 GHz. In addition, another output clock, supporting division by 1, 2, 4, or 8, can be used as a serial readout clock. The PLL has been designed and fabricated in 0.13 μm CMOS technology. The 1024-cycle jitter is approximately 0.013 periods. The area of the PLL core is 0.077 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . The power consumption of the PLL core is 14.5 mW.

A low-power DTOF image sensor with double-frame-multiplexing mode for long-range detection

A novel time-to-digital converter (TDC) operation mode, called double-frame-multiplexing (DFM), is proposed for time-of-flight (TOF) measurements. It is based on the separate detection of the minimum distance and depth of the measured targets, which reduces the power consumption of in-pixel TDCs and expands the maximum detection distance under high resolution. A 64 × 64 direct TOF image sensor chip is fabricated in a 0.18 μm CMOS process. Driven by a 125 MHz multi-phase clock and a 50 MHz data readout clock, the chip achieves a maximum frame rate of 20 kframe/s, a maximum detection distance of 750 m (5 μs), and a maximum depth of field of 3 m (20 ns) with a temporal resolution of 1 ns. The DFM mode reduces the average power consumption to 60 mW without consideration of SPADs. The worst-case measured differential nonlinearity is −0.61/+0.69 least significant bit (LSB) and the maximum integral nonlinearity is −1.06/+0.66 LSB.

A 6‐to‐38Gb/s capture‐range bang‐bang clock and data recovery circuit with deliberate‐current‐mismatch frequency detection and interpolation‐based multiphase clock generation

SummaryThis paper reports a bang‐bang clock and data recovery circuit (BBCDR) with an ultra‐wide capture range. The circuit exhibits automatic frequency capture and phase locking over a wide 6‐to‐38 Gb/s range without using a frequency detector, allowed by a recently proposed deliberate‐current‐mismatch technique. Moreover, we accurately obtain an eight‐phase clock through analog interpolation of quadrature signals over the whole wide frequency range by introducing a tunable capacitor array before an inverter‐based phase interpolator. A 65‐nm prototype of the developed BBCDR occupies an area of 0.07 mm2 and attains a bit error rate of less than 10−12 under a continuously variable input frequency, with a total power consumption of 24.6 mW for a 32‐Gb/s non‐return‐zero input, thus leading to 0.769‐pJ/bit energy efficiency.

Overhauser Sensor Array Based 3-D Magnetic Gradiometer for the Detection of Shallow Subsurface Unexploded Ordnance

The information on the high-precision and multi-directional magnetic gradient is highly relevant to detecting and locating shallow subsurface unexploded ordnance. In this paper, the design of a three-dimensional (3D) Overhauser magnetic gradiometer is presented. Taking the sensor array interferences and working efficiency into account, a time slice overlapping based operating time sequence is devised. A precision narrow-band tuning capacitance network based on a cascaded subdivision strategy is constructed to improve the signal-to-noise ratio (SNR) of free induction decay (FID) signals. Additionally, a frequency measuring approach combining multi-phase clock and multi-channel is developed to suppress counting errors and improve the frequency measuring accuracy of FID signals. The 3D Overhauser magnetic gradiometer’s effectiveness was validated through extensive laboratory and field experiments. The laboratory test results show that the magnetic measuring performance of each sensor from the Overhauser magnetic sensor array is consistent. The proposed 3D Overhauser magnetic gradiometer is able to measure magnetic fields from 20 μT to 100 μT with an indicating error of less than 0.1 nT. The field exploration demonstrates the applicability of the gradiometer for shallow subsurface unexploded ordnance detection within the urban complex electromagnetic surroundings. Overall, this study can provide support for the accurate detection and localization of shallow subsurface unexploded ordnance under strong interference surroundings.

A 7-Bit 7-GHz Multiphase Interpolator-Based DPC for CDR Applications

This paper presents a 7-bit digital to phase converter (DPC) for high speed clock and data recovery (CDR) applications which is capable of generating multi-phase clocks at 7-GHz frequency. Fabricated in a standard 65-nm CMOS technology, the design introduces a modified phase interpolator (PI) and a quadrature phase corrector (QPC) to reduce the effect of the circuit imperfections on the DPC’s resolution and linearity. Employing a 14-GHz quadrature reference clock, the DPC achieves DNL/INL of 0.7/6 LSB respectively while consuming 40.5 mW power from 1.05 V supply.

Multi-Phase Clock Generation for Phase Interpolation With a Multi-Phase, Injection-Locked Ring Oscillator and a Quadrature DLL

We present a high-accuracy, low-jitter, multi-phase clock generator (MPCG) based on a multi-phase, injection-locked ring oscillator (MPIL-ROSC) with a quadrature delay-locked loop (QDLL). The QDLL tunes the ring oscillator (ROSC) self-oscillation frequency ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${f}_{{0}}$ </tex-math></inline-formula> ) and provides it with multi-phase injection signals. The proposed architecture breaks the intrinsic tradeoff between jitter and phase accuracy in two-phase injection-locked ROSCs. The MPCG’s eight-phase output clock drives a 7-bit phase interpolator (PI) for phase and frequency deskew. A 1.2-V 65-nm CMOS MPCG prototype chip has a better-than-1° eight-phase accuracy and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$58.8~\mathrm {fs}_{\mathrm {rms}}$ </tex-math></inline-formula> jitter (integrated from 100 kHz to 1 GHz), while consuming 15.6 mW at 7 GHz, yielding a −252.7-dB figure of merit ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mathrm {FOM}_{\mathrm {jitter}}$ </tex-math></inline-formula> ). The peak-to-peak integral nonlinearity (INL) and the peak-to-peak differential nonlinearity (DNL) of the PI are less than 1.9 and 1.2 LSB, respectively, across a frequency range from 5 to 8 GHz.

A Broadband Spectrum Channelizer With PWM-LO-Based Sub-Band Gain Control

A broadband spectrum channelizer employing pulsewidth-modulated local-oscillator (PWM-LO)-based sub-band amplitude control is demonstrated. The channelizer has an analog bandwidth of 800 MHz and partitions the input spectrum into eight contiguous sub-bands. The design employs an approach based on frequency folding from harmonics of multi-phase periodic clocks and allows for scaling the relative gain of the sub-bands over a 20-dB range. This relaxes the compression performance of the channelizer baseband and sub-analog-to-digital converter (ADC) dynamic range in the presence of large sub-bands. Gain control on individual sub-bands is performed by employing customized PWM-LO waveforms, where the PWM-LO pulses are generated using delay-locked loops (DLLs). Off-chip learning employing a neural network is used to estimate the PWM symbol pulsewidths required for setting the desired LO harmonic levels. A 1.6-GS/s spectrum channelizer integrated circuit (IC) is implemented in a 65-nm CMOS process to verify the architecture. The measured channelizer gain is 51.6–56.5 dB without gain scaling and provides a range of 37–59 dB with PWM-LO gain control. Gain scaling at a specific harmonic improves blocker compression in an unattenuated sub-band from −34 to −16 dBm. The in-band gain compression with gain scaling also increases from −32 to −17 dBm.

Analysis and Comparison of Low-Power 6-GHz N-Path-Filter-Based Harmonic Selection RF Receiver Front-End Architectures

<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$N$ </tex-math></inline-formula> -path switching systems using switched-series R-C networks are analyzed in the context of RF receiver front-ends, and it is shown that it is possible to mitigate the need to generate an accurate low power clock at high frequencies by operating at higher order harmonics of the switching frequency. For values of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$N$ </tex-math></inline-formula> that are an integer factor of 4 (i.e., <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$N$ </tex-math></inline-formula> = 4, 8, and 16), harmonic selection RF receivers’ architectures are presented using two feed-forward <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$N$ </tex-math></inline-formula> -path switching filters and harmonic recombination at the baseband. Moreover, it is demonstrated how the harmonic recombination stage at the baseband can be reconfigured to select the third harmonic of the switching frequency rather than the fundamental to reduce the input frequency and power consumption of the multi-phase clock generator by a factor of 3. In addition, to analyze the performance of the proposed RF receiver architecture, multiple receivers have been designed and post-layout simulated in two CMOS technologies, TSMC 130 nm and TSMC 65 nm. The resulting 5.7–7.2-GHz RF receiver architectures allow for operation at the third harmonic of the LO frequency (i.e., 1.9–2.4 GHz), reducing power consumption and allowing for good performance metrics at both studied technology nodes.

A Study of Digitally Controlled Oscillator Based on Multi-Phase Clock

A Study of Digitally Controlled Oscillator Based on Multi-Phase Clock

A Full-Duplex Receiver With True-Time-Delay Cancelers Based on Switched-Capacitor-Networks Operating Beyond the Delay–Bandwidth Limit

Wideband self-interference cancellation (SIC) in full-duplex (FD) radios requires the achievement of large delays to accurately emulate the SI channel. However, compact, power-efficient, low-loss/noise/distortion nanosecond-scale delays are extremely challenging to achieve on silicon. Passive transmission lines on silicon are lossy and area-intensive and exhibit reduced bandwidths when miniaturized using inductors and capacitors, whereas active approaches are noisy and power-hungry. In this work, we present a technique that leverages switched-capacitor circuits with multiphase clocking to obtain large on-chip delays over wide bandwidths with the low area and power consumption, thus exceeding the delay-bandwidth product (DBW) limits offered by conventional linear time-invariant (LTI) circuits. This technique is demonstrated in an FD receiver with time-interleaved switched-capacitor-based delay cells in RF and BB domains. The FD receiver is implemented in a standard 65-nm CMOS process and operates from 100 MHz-1 GHz with gain tunability of 15-38 dB, a noise figure of 5.4 dB, and power consumption of 31 mW. The RF/BB canceler delay cells have real-/complex-valued weighting with delays ranging from 0.2-1.1 ns/10-75 ns while consuming 25.5 and 6.5 mW, respectively. These large tunable delays perform FIR-filtering-based cancellation, enabling 30-35-dB integrated SI cancellation over 20 MHz on top of an off-the-shelf ferrite circulator when terminated by a dipole antenna (isolation of 22 dB), and can handle TX power of up to +9 dBm. Under SIC, the RF and BB cancelers degrade the RX noise figure by 1.1 and 0.8 dB, respectively.

Design of Pixel Circuit Using a-IGZO TFTs to Enhance Uniformity of AMOLED Displays by Threshold Voltage Compensation

This article presents a novel voltage-programmed pixel circuit using a-IGZO TFTs to effectively compensate threshold voltage (VTH) variations of driving TFT. The compensation is very important to maintain the pixel brightness of active-matrix organic light-emitting diodes (AMOLED) displays. The proposed pixel design uses four-phase clocking schemes: reset period, VTH detection period, data input period and emission period. To maintain uniformity in phases, the duration of all the phases is taken to be same which results in easier design of the multi-phase clock. Moreover, the switching speed of control signals is as high as 25 kHz, ensuring a high frame rate. The circuit has been simulated extensively, and the operation has been verified using SPICE models of a-IGZO TFT and OLED on Cadence Spectre. The circuit also achieves high contrast as OLED does not emit light in any periods except the emission period. The OLED current error in the proposed design for a VTH variation of 170% is below 0.1%. This circuit also provides a high aperture ratio of 51.6%, which ensures high resolution of AMOLED displays.

62.5 ps LSB resolution multiphase clock Time to Digital Converter (TDC) implemented on FPGA

A 13-bit Time to Digital Converter is implemented using multiphase clock technique. Xilinx’s Virtex 5 FPGA platform is used to realize the TDC architecture. One PLL within the FPGA works as a clock synthesizer to multiply the reference clock to 500 MHz. Then the combination of PLL and DLL topologies are used to generate 16 phases of the clock, separated by 11.25°. Further, 16 phases are generated by inverting the first 16 phases. A resolution of 62.5 ps has been recorded. Measured INL and DNL are within 1 LSB. The present work is suitable for many critical applications due to its PVT insensitive and robust properties.

High-precision frequency measurement for microresonant sensors based on improved modified multi-phase clock method.

Microelectromechanical system resonant sensors are widely used in high precision applications. Frequency measurement plays an important role in such frequency readout sensors. This paper proposed an improved modified frequency measurement method based on the multi-phase clock (MPC), which can effectively improve the measurement accuracy but does not reduce the output rate. Innovative claims include (1) building a model of measurement error for MPC in which the probability of triggering error under different conditions is calculated, (2) improving the accuracy of the MPC measurement by phase reverse, and (3) proposing an algorithm to eliminate jitters of the measured signal. We compared the measurement results of this optimized MPC realized by the field programmable gate array (FPGA) device with those of the conventional MPC, spectral measurement, and equal precision measurement implemented with the National Instruments acquisition equipment PXI-4461 and USB-6366, respectively. The results show that the bias instability of the adopted method is ∼10 µHz obtained by Allan variance analysis, which is better than that of the other three methods. It can meet the accuracy requirements for the resonant frequency measurement of state-of-the-art resonant accelerometers. In addition, an algorithm running in FPGA is proposed to eliminate jitters caused by the noise of the measured signal for enhancing the robust of optimized MPC. The results demonstrate that the optimized MPC has features of high accuracy and anti-interference capability and can be easily transferred to the application specific integrated circuit in the future due to its full digital circuit version.

A 52-Gb/s Sub-1-pJ/bit PAM4 Receiver in 40-nm CMOS for Low-Power Interconnects

This article presents a quarter-rate source-synchronous PAM-4 receiver for energy-efficient chip-to-module communication. A novel single-stage multiple peaking continuous-time linear equalizer (MP-CTLE) using feedback enabled multiple peaking scheme for both high-frequency equalization (HF-EQ) and low-frequency equalization (LF-EQ) is proposed to improve the BER performance and overall energy efficiency. The LF-EQ of the MP-CTLE eliminates the need for many DFE taps in SR/VSR applications to save power and area. A 1-tap feedforward equalizer (FFE) is used to further compensate for the high-frequency loss. We also use a ring oscillator based wide bandwidth phase-locked loop (WBW-PLL) as the multiphase clock generator (MPCG) in the clock and data recovery loop to save power with acceptable phase accuracy. Fabricated in 40-nm CMOS technology, the prototype receiver chip achieves error-free operation up to 52 Gb/s PAM-4 with superior bit efficiency of 0.126pJ/bit/s/dB while compensating 7.3-dB channel loss at 13GHz. With the proposed single-stage MP-CTLE, the receiver extends the error-free operation from PRBS-7 to PRBS-9. The BER bathtub curve at $10^{-6}$ is improved from 0.018 UI to around 0.1 UI.

A 32-Gb/s 0.46-pJ/bit PAM4 CDR Using a Quarter-Rate Linear Phase Detector and a Self-Biased PLL-Based Multiphase Clock Generator

This article presents a four-level pulse-amplitude modulation (PAM4) quarter-rate clock and data recovery circuit (CDR). A quarter-rate linear phase detector (QLPD) is proposed to reduce the recovered clock jitter by removing the dithering jitter of the bang-bang PD. A self-biased phase-locked loop (PLL)-based multiphase clock generator (MCG) with a very wide loop bandwidth (around 600 MHz) is proposed to reduce the MCG power consumption and generate a low-jitter multiphase clock for the quarter-rate operation. Fabricated in a 40-nm CMOS process, the prototype achieves a bit efficiency of 0.46 pJ/bit at 32-Gb/s input data rate. The measured jitter tolerance (JTOL) at the bit error rate (BER) of < 10−12 is higher than 0.35 UIPP with the corner frequency at about 10 MHz. The measured integrated jitter of the 4-GHz recovered clock is 352.6 fs.

A 112-Gb/s PAM-4 Long-Reach Wireline Transceiver Using a 36-Way Time-Interleaved SAR ADC and Inverter-Based RX Analog Front-End in 7-nm FinFET

A 36-way time-interleaved 56-GS/s 7-bit ADC is designed to realize 112-Gb/s pulse-amplitude modulation (PAM-4) transceiver in a 7-nm FinFET CMOS. The receiver analog front-end stages and the ADC track-and-hold (T/H) buffers are implemented using inverter-based Gm/inverse-Gm-load cells. A distributed inductor peaking network and multi-phase clock calibration is implemented in the quarter-rate transmitter. The transceiver achieves <1E-8 pseudorandom binary sequence (PRBS)-31 PAM-4 bit error rate (BER) over a channel with 37.5-dB loss at 28 GHz while dissipating 602 mW per channel, excluding DSP.

A 6.4-GS/s 10-b Time-Interleaved SAR ADC with Time-Skew Immune Sampling Network in 28-nm CMOS

This paper presents a 6.4-GS/s 16-way 10-bit time-interleaved (TI) SAR ADC for wideband wireless applications. A two-stage master–slave hierarchical sampling network, which is immune to the time skew of multi-phase clocks, is introduced to avoid the time-skew calibration for design simplicity and hardware efficiency. To perform low distortion and fast sampling at acceptable power consumption, a linearity- and energy efficiency-improved track-and-hold (T&amp;H) buffer with current-feedback compensation scheme is proposed. Accompanied by its low-output-impedance feature, the buffer obtains adequate bandwidth which can cover the entire ADC Nyquist sampling range. Moreover, the split capacitor DAC combined with a novel nonbinary algorithm is adopted in single-channel ADC, enabling a shorter DAC settling time as well as less switching energy. Capacitor mismatch effect with related design trade-off is discussed and behavior models are built to evaluate the effect of capacitor mismatch on ENOB. An asynchronous self-triggered SAR logic is designed and optimized to minimize the delay on logic paths to match up the acceleration on DAC and comparator. With these proposed techniques, the 10-b sub-ADC achieves a 400-MHz conversion rate with only 3.5-mW power consumption. The circuit is designed and simulated in TSMC 28 HPC process and the results show that the overall ADC achieves 54.6-dB SNDR and 58.1-dB SFDR at Nyquist input while consuming 127-mW power from 1-V/1.5-V supply and achieving a Walden FoM of 45[Formula: see text]fJ/conv-step.