Multi-modulus Frequency Divider Research Articles

Pulse swallowing frequency divider with low power and compact structure

A pulse swallowing frequency divider with low power and compact structure is presented. One of the DFFs in the divided by 2/3 prescaler is controlled by the modulus control signal, and automatically powered off when it has no contribution to the operation of the prescaler. The DFFs in the program counter and the swallow counter are shared to compose a compact structure, which reduces the power consumption further. The proposed multi-modulus frequency divider was implemented in a standard 65 nm CMOS process with an area of 28 × 22 μm2. The power consumption of the divider is 0.6 mW under 1.2 V supply voltage when operating at 988 MHz.

Quantization Noise Suppression in Fractional-$N$ PLLs Utilizing Glitch-Free Phase Switching Multi-Modulus Frequency Divider

A novel programmable frequency divider for quantization noise (QN) suppression in fractional-N phase-locked loops (PLLs) is presented in this paper. The proposed phase switching multi-modulus frequency divider (PS-MMFD) utilizes a novel glitch-free phase switching (PS) divide-by-0.5/1/1.5/2 cell to reduce the frequency division step to 0.5 and its QN induced by ΔΣ modulation is thus suppressed by additional 6 dB. Compared with other frequency dividers used for QN suppression, the proposed glitch-free PS-MMFD is more robust, can operate at higher input frequency and consumes less power. Detailed analysis and implementation of the proposed glitch-free PS-MMFD is demonstrated, followed by experimental results from a fully integrated ΔΣ fractional-N PLL utilizing the proposed QN suppression technique. Implemented in a 0.18 μm CMOS process, the proposed glitch-free PS-MMFD occupies an area of 0.38 mm × 0.25 mm and consumes 5 mA from a 1.8-V supply at an input frequency of 2 GHz. Measurement results also demonstrate the additional 6-dB QN suppression by the proposed technique.

A 470-$\mu{\hbox {W}}$ 5-GHz Digitally Controlled Injection-Locked Multi-Modulus Frequency Divider With an In-Phase Dual-Input Injection Scheme

This paper presents a digitally controlled injection-locked multimodulus frequency divider (ILMFD) based on a ring-oscillator using inverter chains for a small area and low power consumption. In the proposed ILMFD, division ratios of 2, 3, 4, 5 and 6 are achieved by using a programmable delay line that changes the self-oscillation frequency of the ring-oscillator. The locking range of the proposed ILMFD is improved by employing a dual-input injection scheme, which unlike previous multiinput injection schemes, does not require distinct phase inputs. A prototype chip implemented in a 0.13- <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex Notation="TeX">$\mu{\hbox {m}}$</tex></formula> CMOS process has an area of <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$35\times 33\ \mu{\hbox {m}}^{2}$</tex></formula> and operates at 5 GHz while consuming 470 <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$\mu{\hbox {W}}$</tex></formula> from 1.2 V supply, where 350 <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$\mu{\hbox {W}}$</tex></formula> is dissipated in the core of the ILMFD. The proposed divider is the first reported multimodulus ILFD with digitally controlled division ratios and an in-phase dual-input injection scheme.

Low power design of multi-modulus programmable frequency divider

A novel low power multi-modulus programmable divider is presented. It employs the division ratio control-bits (DRCBs) to cut off the current of certain latches on occasion, which then have no contribution to the operation of the entire divider. The proposed structure allows a power reduction up to 50%.

A monolithic sigma-delta fractional-N frequency synthesizer with implicit dual-path filter and phase switching multi-modulus frequency divider

A fully integrated Sigma-delta fractional-N frequency synthesizer is realized in TSMC 0.18 μm MM/RF 1P6M Salicide 1.8V/3.3V technology. The proposed implicit dual-path loop filter with enhanced trans-conductor can eliminate the charge pump mismatch of the conventional dual-path loop filter and suppress the effect of parasitic poles and zero as well as reduce the area of the loop filter. A simple frequency divider based on phase switching technique is employed to reduce the area and power dissipation. The frequency synthesizer consumes 21 MW power from 1.8 V power supply voltage with area 1.80 × 2.0 mm2. The achieved phase noise is ?82 dBc/Hz at 10 kHz offset, ?108 dBc/Hz at 100 kHz offset and ?128 dBc/Hz at 1 MHz offset respectively with frequency switching time 95 μs.

A Multigigahertz Multimodulus Frequency Divider in 90-nm CMOS

This brief presents a multimodulus frequency divider with division ratio between 64 and 127 fabricated in 90-nm CMOS. By using a load-switching technique, high operating frequency, and low power static divider was achieved. The divider consists of six 2/3 divider stages. The maximum operating frequency is 4.7 GHz with current consumption 2.3 mA at low voltage supply 1.2 V and rms cycle-to-cycle jitter lower than 1 ps

A 2-V, 1.8-GHz BJT phase-locked loop

This paper describes the design of a bipolar junction transistor phase-locked loop (PLL) for /spl Sigma//spl Delta/ fractional-N frequency-synthesis applications. Implemented in a 0.8-/spl mu/m BiCMOS technology, the PLL can operate up to 1.8 GHz while consuming 225 mW of power from a single -2-V supply. The entire LC-tuned negative-resistance variable-frequency oscillator is integrated on the same chip. A differential low-voltage current-mode logic circuit configuration is used in most of the PLL's functional blocks to minimize phase jitter and achieve low-voltage operation. The multimodulus frequency divider is designed to support multibit digital modulation. The new phase and frequency detector and loop filter contain only npn transistors and resistors and thus achieve excellent resolution in phase comparison. When phase locked to a 53.4-MHz reference clock, the measured phase noise of the 16-GHz output is -91 dBc/Hz at 10-kHz offset. The frequency switching time from 1.677 to 1.797 GHz is 150 /spl mu/s. Die size is 4300/spl times/4000 /spl mu/m/sup 2/, including the passive loop filter.