Multi-level Phase Change Research Articles

Role of interfaces on the stability and electrical properties of Ge2Sb2Te5 crystalline structures

GeSbTe-based materials exhibit multiple crystalline phases, from disordered rocksalt, to rocksalt with ordered vacancy layers, and to the stable trigonal phase. In this paper we investigate the role of the interfaces on the structural and electrical properties of Ge2Sb2Te5. We find that the site of nucleation of the metastable rocksalt phase is crucial in determining the evolution towards vacancy ordering and the stable phase. By properly choosing the substrate and the capping layers, nucleation sites engineering can be obtained, thus promoting or preventing the vacancy ordering in the rocksalt structure or the conversion into the trigonal phase. The vacancy ordering occurs at lower annealing temperatures (170 °C) for films deposited in the amorphous phase on silicon (111), compared to the case of SiO2 substrate (200 °C), or in presence of a capping layer (330 °C). The mechanisms governing the nucleation have been explained in terms of interfacial energies. Resistance variations of about one order of magnitude have been measured upon transition from the disordered to the ordered rocksalt structure and then to the trigonal phase. The possibility to control the formation of the crystalline phases characterized by marked resistivity contrast is of fundamental relevance for the development of multilevel phase change data storage.

Multilevel data storage in multilayer phase change material

Superlattice-like GaSb/Sb4Te phase change film was proposed for multilevel phase change memory with the feature of three stable resistance states. Two distinct transition temperatures of around 170 and 230 °C were observed in the superlattice-like GaSb/Sb4Te thin film. Under elevated temperature, the precipitated rhombohedral Sb phase was found in the Sb4Te layer, which was followed by the crystallization of rhombohedral Sb2Te3, whereas the GaSb layer remained almost in the amorphous state except the impinged Sb grains. The formation of percolation path for crystallization in the GaSb layer can account for the multilevel resistance states. For the GaSb/Sb4Te-based device, the reversibly electrical switching was realized under the electrical pulse as short as 10 ns, and the endurance was achieved at least 105 cycles among different resistance states.

Implementation of time-aware sensing technique for multilevel phase change memory cell

This paper introduces and tests a time-aware sensing scheme to overcome the drift issue in Multi-Level Phase Change Memory (MLPCM). Adaptive resistance thresholds are calculated based on statistical data to generate timely reference levels for comparison. Simulations are carried out utilizing MLPCM cell model that mimics the physical behavior of MLPCM cell. The simulation results were then compared against experimental data, and it was noted that simulation results of the used MLPCM model are in close agreement with the experimental data. Furthermore, the time aware sensing scheme provided an accurate reading of the stored bit values given that the timely reference levels successfully compensated for the drift phenomenon. Finally, an application of time aware sensing coupled with MLPCM was implemented, where MPLCM is used as memory element in a Look Up Table (LUT). The suggested MLPCM based LUT utilizes the density and reliability offered by MLPCM paired with the presented time aware sensing scheme.

Toward Multiple-Bit-Per-Cell Memory Operation With Stable Resistance Levels in Phase Change Nanodevices

Resistance drift of the amorphous states of multilevel phase change memory (PCM) cells is currently a great challenge for the commercial implementation of a reliable multiple-bit-per-cell memory technology. This paper reports observation of a stable intermediate state for a multilevel PCM cell that is achieved through nonuniform heating with a square current injection top electrode. Drift coefficient of the intermediate state is an order of magnitude lower than reset and has weaker temperature dependence. Using finite-element simulations and an analytical model for the subthreshold current–voltage characteristics, based on thermally activated hopping of charge carriers across Coulombic donor-like traps, we conclude that the defect density is two orders of magnitude larger in the intermediate state. We attribute the low drift coefficient of the intermediate state to a large number of stable interfacial defects which dominate the electron transport. Current findings give way to a more stable ultrahigh-density PCM device.

A 15 µm-Pitch, 8.7-ENOB, 13-Mcells/sec Logarithmic Readout Circuit for Multi-Level Cell Phase Change Memory

This paper presents a narrow-pitch readout circuit for multi-level phase change memory (PCM) employing an architecture of two-step 5 bit logarithmic ADC. A single-slope-architecture based fine ADC yields a 15 $\mu$ m-width compact single channel readout circuit for column parallel readout structure. A current-mode 2 bit flash ADC for coarse conversion and the pipelined architecture between the coarse and fine conversion enhance the readout rate up to 13 Mcells/sec. With the enhanced residue accuracy provided by the replica circuit of residue generator, the ADC achieves excellent linearity of 9.96 b (linear ADC equivalent). The integration-based residue generation effectively reduces circuit noise and yields 8.7 ENOB. The prototype chip was fabricated in a 65 nm CMOS process and the measured power consumption from a single channel readout circuit was 105 $\mu$ W at 13 Mcells/sec conversion rate at 1.2 V supply.

Non-Binary Orthogonal Latin Square Codes for a Multilevel Phase Charge Memory (PCM)

This manuscript proposes non-binary orthogonal Latin square (OLS) codes that are amenable to a multilevel phase change memory (PCM). This is based on the property that the proposed ( n symbols, k symbols) t -symbol error correcting code uses the same H matrix as an ( n bits, k bits) binary t -bit error correcting OLS code. The new codes are shown to have a shorter check bit length and better probability in encoding/decoding than conventional binary OLS codes. Extensive results are provided for assessment and comparison. The proposed codes are also shown to be always better than the matrix codes, i.e. independently of the metric and the parameters employed in the comparison.

Multi-Level Lateral Phase Change Memory Based on N-Doped Sb70Te30 Super-Lattice like Structure

Lateral phase change memory (PCM) has attracted a lot of interest due to its simpler fabrication process and lower current. Researchers are trying to increase the storage capacity of lateral PCM. This paper proposed a novel super-lattice like (SLL) structure for lateral PCM to achieve multi-level storage. Lateral PCM with SLL structure incorporated with N-doped Sb70Te30 and ZnS-SiO2 has been fabricated and tested. Both tested static I-V curve and dynamic pulse mode R-V curve show multi states existing in the device. Electrical and thermal simulations have been done for this device. Simulation results show that different resistance level can be found in this device with different states of phase change bridges. With increasing periods of SLL structure, more states can be achieved.

A Temperature Tracking Read Reference Current and Write Voltage Generator for Multi-Level Phase Change Memories

A Temperature Tracking Read Reference Current and Write Voltage Generator for Multi-Level Phase Change Memories

Polarization readout analysis for multilevel phase change recording by crystallization degree modulation

Four different states of Si15Sb85 and Ge2Sb2Te5 phase change memory thin films are obtained by crystallization degree modulation through laser initialization at different powers or annealing at different temperatures. The polarization characteristics of these two four-level phase change recording media are analyzed systematically. A simple and effective readout scheme is then proposed, and the readout signal is numerically simulated. The results show that a high-contrast polarization readout can be obtained in an extensive wavelength range for the four-level phase change recording media using common phase change materials. This study will help in-depth understanding of the physical mechanisms and provide technical approaches to multilevel phase change recording.

Superlattice-like Sb50Se50/Ga30Sb70 thin films for high-speed and high density phase change memory application

Multi-level phase change character of superlattice-like (SLL) Sb50Se50/Ga30Sb70 thin films was investigated through in-situ film resistance measurement. SLL structure of the thin films was confirmed by using transmission electron microscopy. Three resistance states were observed during heating process, and their thermal stability was also examined. A picosecond laser pump-probe system was used to measure phase-change time of the SLL Sb50Se50/Ga30Sb70 thin films. Phase change memory cells based on the SLL [SS(5 nm)/GS(10 nm)]3 thin films were fabricated to test and verify multi-level switch between set and reset states.

×10 Fast write, 80% energy saving temperature controlling set method for multi-level cell phase change memories to solve the scaling blockade

This paper presents a new set method with temperature control to reduce both energy dissipation and write time of multi-level cell (MLC) phase change memories (PCMs). Since the set energy of PCM is quite larger than reset due to long set time, reducing the set energy is a critical issue to realize MLC PCM. Moreover, this paper shows the set time and energy become longer and lager as the diameter of a tungsten heater is scaled down due to thermal dissipation. To solve these problems, this paper proposes a unique set pulse which combines two pulses: the 1st pulse is high voltage and short width and the 2nd pulse is low voltage and long width. The 1st pulse contributes to faster set time and the 2nd pulse controls the crystallization of GST film. As a result, ∼80% of energy saving and ∼10-times fast write speed are achieved for a 90nm MLC PCM. The proposed set method overcomes the scaling blockade due to thermal dissipation and is essential for a nano-scale MLC PCM.

Two-bit multi-level phase change random access memory with a triple phase change material stack structure

This work demonstrates a novel two-bit multi-level device structure comprising three phase change material (PCM) layers, separated by SiN thermal barrier layers. This triple PCM stack consisted of (from bottom to top), Ge2Sb2Te5 (GST), an ultrathin SiN barrier, nitrogen-doped GST, another ultrathin SiN barrier, and Ag0.5In0.5Sb3Te6. The PCM layers can selectively amorphize to form 4 different resistance levels (“00,” “01,” “10,” and “11”) using respective voltage pulses. Electrical characterization was extensively performed on these devices. Thermal analysis was also done to understand the physics behind the phase changing characteristics of the two-bit memory devices. The melting and crystallization temperatures of the PCMs play important roles in the power consumption of the multi-level devices. The electrical resistivities and thermal conductivities of the PCMs and the SiN thermal barrier are also crucial factors contributing to the phase changing behaviour of the PCMs in the two-bit multi-level PCRAM device.

Multi-Level Phase Change Memory Cells with SiN or Ta2O5 Barrier Layers

This work compares the effects of SiN and Ta2O5 barrier layers in a multi-level phase change random access memory (PCRAM) cell. The PCRAM cell comprises a phase change material stack between a top and a bottom electrode. The phase change material stack comprises a nitrogen-doped Ge2Sb2Te5 (NGST) layer on top of a thin barrier layer on an undoped GST layer. The thermal conductivity and electrical resistivity of the barrier layer affect multi-level switching performance in terms of endurance as well as power consumption. Extensive electrical characterization was performed on these PCRAM multi-level devices. Thermal analysis was also performed to investigate the thermal efficiency of each barrier layer. It was observed that for a constant barrier layer thickness of 1.5 nm, the endurance of the multi-level device with the SiN barrier layer was better than that with the Ta2O5 barrier layer; however, the multi-level device with the Ta2O5 barrier layer had a lower power consumption than that with the SiN barrier layer.

Multi-Level Phase Change Memory Cells with SiN or Ta2O5Barrier Layers

Multi-Level Phase Change Memory Cells with SiN or Ta₂O₅Barrier Layers

Multi-level phase change memory devices with Ge2Sb2Te5 layers separated by a thermal insulating Ta2O5 barrier layer

This work investigates multi-level phase change random access memory (PCRAM) devices comprising two Ge2Sb2Te5 (GST) layers sandwiching a thermal insulating Ta2O5 barrier layer. The PCRAM cell comprises a phase change material stack between a top and a bottom electrode. The phase change material stack comprises a nitrogen doped GST (NGST) layer on a thin Ta2O5 barrier layer on an undoped GST layer. It is demonstrated that one of the phase change layers in the GST stack can be selectively amorphized by using a voltage pulse. This enables multi-level resistance switching. The differences in resistivities, as well as the different melting and crystallization temperatures of both the NGST and GST layers, contribute to the multi-level switching dynamics of the PCRAM device. The thermal conductivity of Ta2O5 with respect to GST is also another factor influencing the multi-level switching. Extensive electrical characterization of the PCRAM devices was performed. Thermal analysis was used to examine the physics behind the multi-level switching mechanism of these devices.

Fabrication of multi-level switching phase change nano-pillar device using InSe/GeSbTe stacked structure

The InSe/GeSbTe stacked phase change materials were investigated at nano-scale for multi-level switching with a large sensing margin and fast switching. The 200 nm nano-pillar devices of InSe material and InSe/GeSbTe materials were fabricated using NIL, and its electrical properties were characterized using conducting AFM system, that was connected to a pulse generator and a voltage source. In case of InSe based nano-pillar device, it was evaluated that the fast switching speed (<100 ns) and large difference of resistance on–off ratio (>10,000) and exhibited only bi-level switching characteristics. In case of the InSe/GeSbTe PCMs structure exhibited three levels of resistance state with a few hundred times of difference between them with 100 ns reset pulse.