Multilevel Inverter Topology Research Articles

Enhancing Reliability in Multilevel Inverter: A Fault‐Tolerant Approach With Reduced Switch Count

ABSTRACTReliability is a major concern in multilevel inverters (MLI) due to the increased number of power switches and diodes, which increases the chance of switch failures and complicates the inverter design. The primary challenges faced by the current MLI design include higher control complexity, increased parasitic elements, more extensive protection, and lack of multiple fault tolerance. Therefore, developing reduced switch MLI with fault‐tolerant ability is crucial to ensure system availability and prevent adverse outcomes. To address these challenges, this article introduces a highly resilient fault‐tolerant reduced switch count (FTRSC) MLI topology offering fault tolerance with minimal switch count. The proposed topology provides fault tolerance in case of single‐ and multiple‐switch open‐circuit (OC) failures. The inherent fault‐tolerant operation is analyzed for the proposed topology's symmetric and asymmetric configurations. The simulation and experimental results validate the effectiveness of the proposed topology considering normal, faulty, and postfault conditions. Furthermore, the reliability evaluation of the proposed work is carried out using the Markov chain model, resulting in a high total mean time to failure of approximately 117,550 h/failures, along with an efficiency of 96.3%. These findings demonstrate that the proposed circuit has enhanced reliability and extended mean time to failure, affirming its suitability for sensitive industrial applications. Finally, a thorough comparison with recent studies highlights the superiority of the proposed system.

Traditional and Hybrid Topologies for Single-/Three-Phase Transformerless Multilevel Inverters

With increasing interest in integrating solar power into the utility grid, multilevel inverters are gaining much more attention for medium- and high-power applications due to their high-quality waveform, low voltage stress across active components, and low total harmonic distortion in output voltage. However, to achieve these benefits, a large number of active and passive components are required. A transformer is also required to provide galvanic isolation, which increases its size and weight and reduces its power density and efficiency. In order to overcome the disadvantages posed by transformer-based inverters, research is being conducted on the transformerless topology of multilevel inverters. The first aim of this review article is to summarize traditional transformerless multilevel inverters (TMLIs) considering both single- and three-phase topologies. Secondly, the main aim of this article is to provide a detailed overview of the hybrid topologies of TMLIs that employ fewer components for photovoltaic applications. In addition, this study compares traditional and hybrid single-/three-phase topologies in terms of component count and performance factors, which will be useful to researchers.

Review of recent trends of advancements in multilevel inverter topologies with reduced power switches and control techniques

AbstractCurrently, multilevel inverters (MLI) are comprehensively used to integrate renewable energy sources with the grid or high‐power applications. MLI has outstanding properties such as high‐level output voltage with tremendous power quality and negligible harmonics distortion. General MLI topologies have a more complex circuit, high overall cost and installation area. Due to a large number of power switches and isolation of control circuit, fewer power electronic switches and DC source along with its suitable control logic is the need of the hour. Therefore, a lot of research scope exists in this area. Here, some of the topologies with a fewer number of power switches are reviewed and scrutinized. An extensive analysis of the topologies, control strategy and applications are presented here, suggesting suitable multilevel inverter solutions to the known industrial application or new research.

Open-Circuit Fault-Tolerant High-Gain Multilevel Inverter Topology With Minimum of 2/3 Level in Postfault Condition

Open-Circuit Fault-Tolerant High-Gain Multilevel Inverter Topology With Minimum of 2/3 Level in Postfault Condition

An innovative 11-level multilevel inverter topology with rotating trapezoidal SPWM for industrial and renewable applications

This paper provides a new, less complex multilevel inverter topology that can be used for industrial loads and renewable energy sources. The arrangement consists of eight switches to produce an 11-level output voltage with two uneven input sources. Moreover, it can be connected in a cascade to increase the output voltage and number of levels even further. Due to its control mechanism, which is based on the Rotating Trapezoidal Sinusoidal Pulse Width Modulation control method for creating a high-quality output voltage, the inverter’s key characteristic is its very low harmonic distortion of 3.45% at the output voltage when compared to the advanced triangular carrier-based PWM techniques of phase disposition sinusoidal pulse width modulation (PD-SPWM) it produces harmonic distortion of 11.38% at the output voltage, phase opposition disposition sinusoidal pulse width modulation (POD-SPWM) it produces harmonic distortion of 6.43% at the output voltage, alternative phase opposition disposition sinusoidal pulse width modulation (APOD-SPWM) it produces harmonic distortion of 6.69% at the output voltage, IN-Shift sinusoidal pulse width modulation (IN-shift SPWM) it produces harmonic distortion of 3.93% at the output voltage. This inverter is commonly used in wind turbines and solar cells. The schemes are implemented in MATLAB/SIMULINK and are validated with single-phase 11-level inverter implemented by using digital signal controller (DSC).

Reduced switch single source multilevel inverter topology for renewable photovoltaic system applications

Reduced switch single source multilevel inverter topology for renewable photovoltaic system applications

Machine learning based fault detection technique for hybrid multi level inverter topology

AbstractMultilevel inverters (MLIs) have a significant contribution in many industrial sectors due to their improved power quality and lesser voltage stress, over the conventional three‐level inverters. However, the implementation of MLIs with an increased device count creates the scope of development in MLIs topologies. In this regard, a hybrid MLI topology is studied in this paper whose architecture is based on conventional two‐level inverters. This topology has lesser device count characteristics when compared to conventional and most of the recently presented configurations for nine‐level output voltage generation. The major issue of capacitor voltage balancing is resolved by employing an appropriate switching strategy. However, the semiconductor switches are the most vulnerable components and causes the open circuit faults frequently that creates issues in real time operation. Hence, it is important to detect the open circuit fault in switches in the least possible time. A new approach to open circuit fault detection technique based on the analysis of load voltage waveform is proposed in this paper. The wavelet transform technique has been implemented for feature extraction of load voltage. Later, the classification of the fault has been achieved by training an artificial neural network (ANN). The proposed work has been studied in MATLAB/simulation and the obtained results are verified experimentally.

A level shift carrier based SPWM for reduced switch 5-level multilevel inverter topology

A level shift carrier based SPWM for reduced switch 5-level multilevel inverter topology

Modelling and Simulation of Crisscross Switched Multilevel Inverter Using Cascaded Semi-Half-Bridge Cells

A new cascaded multilevel inverter (MLI) is presented. This MLI aims to use a lesser number of switches, achieve better modularity, and reduce voltage stress. The new structure can operate in symmetric and asymmetric modes, producing all odd and even voltage levels. It comprises semi-half-bridge cells connected in series with crisscross switches to generate target voltage levels for synthesizing the sinusoidal output waveform. An extended version of the proposed MLI topology cascades sub-inverters to generate more voltage levels with reduced standing voltage. Compared to the cascading H-bridge topology, the proposed MLI and its extended version use fewer semiconductor switches. The MATLAB R2013b-based simulation results, confirm the efficacy of the proposed MLI topology.

A new fault-tolerant converter for renewable energy applications with improved reliability

With power converters consisting of several components, the reliability of a power converter becomes a major concern. With a switched-capacitor (SC) integrated into multilevel inverter (MLI) topologies, the chances of faults is more due to a much larger number of components than the MLI topologies with multiple isolated dc voltage sources. In this article, several SC-based 5L-MLI topologies have been analyzed for their performance with open-circuit fault (OCF), and based on the analysis, three 5L fault-tolerant MLI topologies have been proposed. The analysis for the proposed topologies have been carried out in terms of power loss analysis using PLECS software and power quality analysis using MATLAB software for different fault case scenarios. Further, the proposed 5L topologies have been compared with a similar state-of-the-art. A hardware prototype has been developed, and results have been discussed for various operating conditions.

Wild horse optimization algorithm implementation in 7-level packed U-cell multilevel inverter to mitigate total harmonic distortion

Introduction. Multilevel inverters (MLIs) are a popular industrial and, more especially, renewable energy application solution. This is because of its appetite for filters, low distortion class, and capacity to provide a multilayer output voltage that resembles a pure sine waveform. The novelty is in applying the wild horse optimization algorithm (WHOA) to adjust the sinusoidal pulse width modulation (SPWM) technique by producing the optimal reference signal parameters in a new multilevel inverter architecture known as the packed U-cell multilevel inverter (PUC-MLI). Purpose. This study helps with the idea of new inverter architecture and a modified pulse width modulation (MPWM) method to make the multilevel inverter smaller, cheaper, and with less total harmonic distortion (THD). Methods. We use the proposed approach to control a 7-level, single-phase PUC-MLI. The WHOA is used to discover the optimal parameters of the additional reference sine signal after being compared with SPWM to evaluate its performance in harmonic reduction. The simulation’s outcome was validated by building a PUC-MLI prototype. Results. Experimental results and simulations validate the effectiveness of the suggested approach. The WHOA-improved MPWM approach achieves a significant reduction in THD on the PUC-MLI output voltage, as indicated by the results. Practical value. THD in MLI output voltage will be reduced without spending any cost. The suggested solution works with many MLI topologies with varying output voltage levels. References 20, tables 6, figures 12.

Design and performance evaluation of a novel modular asymmetrical multilevel inverter with minimal switches

In the present scenario, emerging topologies in the area of Asymmetrical Multilevel Inverter (AMLI) with fewer power switches and voltage sources have been received greater attention to achieve higher levels with low THD and voltage stress. The present work proposes a novel modular AMLI topology to generate 7-level and 15-level in the output voltage. This topology needs minimal components in comparison of topologies reported in literature. Simulation of the 7-level and 15-level AMLI is performed using MATLAB to generate all the desired levels in the output voltage for different operating frequencies and different modulation indexes. Further, a comparison of the suggested topology with other similar multilevel inverter (MLI) topologies has also been performed on the basis of number of drivers, number of DC sources, levels in the output voltage and power switches. Furthermore, efficiency, losses and total harmonic analysis of 7-level and 15-level AMLI have been calculated and compared with other studies. Finally, simulation results are validated on a hardware set up of the proposed inverter using Opal-RT 4510 controller.

A new multilevel inverter topology, controlled by the pulse width and height modulation (PWHM) technique, with a reduced number of switches

A new multilevel inverter topology, controlled by the pulse width and height modulation (PWHM) technique, with a reduced number of switches

Performance Investigation of 17 Level Reduced Switch Count Multilevel Inverter

The primary objective of this paper is to introduce a 17-level multilevel inverter with only eight power switches and three diodes that can be suitable for electric vehicle applications. This setup utilizes three distinct unequal DC sources to create the 17 levels of output voltage waveforms. The modes of operations of the proposed topology have been discussed in detail. The calculation of conduction losses, switching losses, efficiency, total standing voltage, and cost function per level for the suggested inverter has been elaborated. Due to more semiconductor power switches, diodes, capacitors, driver circuits, and DC sources in typical inverters, switching losses, costs, and harmonic distortion are increased. The nearest-level control technique has been utilized to control the switching elements of the recommended configuration. The performance comparison of various multilevel inverter topologies has also been discussed. The suggested multilevel inverter provides a higher efficiency of 98.60%, cost function of 3.6 for a weight coefficient of 1, improved power quality, and higher reliability. A reduction in the power switches significantly reduces the convolution of switching circuitry. The total harmonic distortion produced by this inverter is 3.49%, which comes under the IEEE standard of 5%.

A Method for Reducing DC Offset Currents Caused by Operating Point Changes in Dual Active Bridge Converter with Multilevel Inverter Topology

A Method for Reducing DC Offset Currents Caused by Operating Point Changes in Dual Active Bridge Converter with Multilevel Inverter Topology

Comparative Analysis of 5-Level and 7-Level Single-Phase Cascaded H-bridge Multilevel Inverters

The demand for high-performance, efficient, and reliable power electronic systems has been steadily increasing in various industrial applications, including renewable energy systems, electric vehicles, and smart grids. In response to this demand, the Cascaded H-Bridge Multi-level Inverter (CHB-MLI) has emerged as a promising solution, offering advantages such as improved voltage waveform quality, reduced harmonic distortion, and enhanced power handling capabilities. The CHB-MLI is characterized by its modular structure, comprising multiple H-bridge cells cascaded in series. Each H-bridge cell operates with a separate DC power source, enabling the generation of stepped voltage levels at the inverter output. By intelligently controlling the individual H-bridge cells, the CHB-MLI achieves the synthesis of a high-quality multilevel output voltage waveform. The different multi-level inverter topologies are Diode-Clamped MLI, Capacitor-Clamped MLI and Cascaded H-bridge MLI. This paper focused on key aspects like design, simulation, control strategies, performance evaluation, overall comparison and analysis of 5-level and 7-level CHB-MLIs. By addressing these aspects, this paper aimed to contribute to the advancement of power electronics technology and promote the adoption of the CHB-MLI in real-world applications, fostering energy efficiency and sustainability in power conversion systems. Index Terms: Inverter, Multi-level inverter, CHBMLI, switching, SPWM, MCSPWM, gate signal, waveform, harmonics, THD, MATLAB.

Solar PV based seventeen level reduced switch symmetrical multilevel inverter topology fed induction motor

Multilevel inverters have received a lot of interest in recent years due to their ability to deliver more voltage levels than typical two-level inverters. Because of this property, multilevel inverters can produce output waveforms that closely resemble sinusoidal waveforms, lowering harmonic distortion dramatically. The emergence of reduced switch symmetrical multilevel inverter topologies has developed the curiosity of many different power conversion systems. These new topologies offer numerous advantages, including greater output voltage quality, fewer harmonic distortions, and increased power conversion efficiency. The inclusion of these inverters in the feeding of induction motors is one of their many prominent uses. A 17 levels of multi-level inverter (MLI) topology is presented with reduced switch count and harmonic reduction for power quality improvement. The inverter is fed by isolated equal photovoltaic panels which act as direct current or DC source. To reduce complexity, switching pulses are generated using hybrid pulse width modulation technique which is designed as controller. Through the use of MATLAB/Simulink, the performance assessment of a unique cascaded multilevel inverter-based reduced switch symmetrical inverter feeding an induction motor drive has been verified. The harmonic distortion with reduced switches obtained is 7.47% which is comparatively less than when compared with conventional cascaded H-bridge topology.

Enhancing power conversion efficiency in five-level multilevel inverters using reduced switch topology

This paper presents extensive research on improving the power conversion efficiency of five-level multilevel inverters (MLIs) by utilizing a reduced switch topology. MLIs have received an abundance of focus because of their ability to generate high-quality output waveforms and have better harmonic outcomes than traditional two-level inverters. The high number of switches in MLIs, on the other hand, can result in increased power losses and lower overall efficiency. In this paper, a novel reduced switch topology for five-level MLIs, which is having five switches is proposed with the aim of minimizing power losses while preserving superior performance due to lesser number of switches. To achieve efficient power conversion, the proposed topology employs advanced pulse width modulation control strategies and optimized switching patterns. The simulation results show that the minimized switch topology improves the power conversion efficiency of the five-level MLI, resulting in lower losses and better overall system performance. The total harmonic distortion (THD) value of the output current has been reduced to 7.12% and the efficiency has been achieved to 96.92%. The findings of this investigation help to advance MLI technology, allowing for more efficient and reliable power conversion in a variety of applications such as renewable energy systems, electric vehicles, and industrial drives.

Performance evaluation of novel 9-level RSMLI topology for grid-tied solar-PV system

The shortage of traditional fossil fuels like coal, petrol and natural-gas are increased day-by-day, fulfills the most of energy demand. Most of engineers are trying to maximize the energy demand by employing renewable energy with existing micro-grid system. Owing to merits, the solar-PV system plays a significant alternative among all other renewable energy sources due to abundant and virtuous nature. For grid-tied solar-PV system, the cascaded H-bridge multilevel inverter is the most significant over the classical 2-level inverter due to provision of isolated input DC sources. But the cascaded H-bridge topology is designed for limited voltage levels due to its larger number of switches for higher voltage levels, high cost, large-size, and more weight. To alleviate these demerits, a reduced-switch multilevel inverter has been generally preferable for higher voltage levels. In this work, a novel 9-level reduced-switch multilevel inverter (RSMLI) topology has been proposed by utilizing low number of switching devices. The performance of proposed novel 9-level RSMLI topology has been verified in grid-tied solar-PV system by using MATLAB/Simulink tool, simulation results are presented with attractive comparisons.

Performance analysis for induction motor fed by reduced switch symmetrical multilevel inverter topology

Due to its capacity to supply more voltage levels than conventional 2-level inverters, multilevel inverters have attracted a lot of attention in recent years. Multilevel inverters may produce output waveforms that nearly approximate sinusoidal waveforms because to this characteristic, which also significantly lowers harmonic distortion. In many different power conversion systems, the introduction of reduced switch symmetrical multilevel inverter topologies has drawn significant interest. Numerous benefits, such as higher output voltage quality, reduced harmonic distortions, and increased power conversion efficiency, are provided by these novel topologies. The inclusion of these inverters in the feeding of induction motors is one of their many prominent uses. In this paper, a generalized topology is presented that generates nine levels using nine switching devices. To reduce complexity, switching pulses are generated using a low frequency pulse width modulation technique. MATLAB/Simulink is used to analyze the performance assessment of a unique three-phase symmetric cascaded multilevel inverter-based reduced switch symmetrical inverter fed induction motor drive, brushless DC (BLDC) motor and grid has been verified. According to the findings the total harmonic distortion (THD) is found to be 15% for a three-phase system and as the number of levels increases to 17 level the THD is 7.10%.