Multilevel Inverter Configuration Research Articles

Seven-Level Symmetrical Series/Parallel Multilevel Inverter with PWM Technique Using Digital Logic

This paper attempts to come up with a proposed configuration of Multilevel inverters with a lesser number of switches that are smaller in size, lesser in cost and with a higher efficiency. Designing an inverter topology with a lesser number of switches and proper control technique is the major challenge. cascaded H-Bridge (CHB) topology are more popular among the existing configurations of multilevel inverters (MLI). Even though it can produce more levels, it needs to accommodate a huge number of switches for higher levels. The focus of this paper is to reduce the number of components for the same voltage level of cascaded H- Bridge configuration. In addition to that, generating the gating pulses for the switches is difficult when there is an asymmetry in the switches. A new symmetrical series/parallel configuration is proposed with reduced switch count and the pulse width modulation (PWM) technique is implemented with digital logic to generate the required gating pulses for the switches. The total harmonic distortion (THDI) of the output current is reduced with this PWM technique. The simulation has been carried out in MATLAB/Simulink software for both R (resistive) and R-L (resistive -inductive) loads.

FPGA-Based Reduced Switch Novel Infinite-Level Inverter

The evolution of multi-level inverters (MLIs) has led to an increase in their efficiency and reliability. This paper demonstrates an FPGA-based reduced switch novel Infinite-Level Inverter. Conventional two-level Voltage Fed Inverters (VFI) suffer from reduced efficiency, greater voltage distortion and higher switching losses. Multi-level inverters (MLI) outweigh the conventional inverter in terms of improved voltage profile, reduced switching losses, increased efficiency and lower component count. This paper demonstrates an FPGA-based Reduced Switch Novel Infinite-Level Inverter that achieves infinite voltage output levels; with a reduced count of passive and active elements. The proposed inverter has a high DC-link utilization factor of 1.23, reduced blocking voltage and inverter switching losses, employing a single DC source and least number of components. It outputs a sinusoidal voltage with a minimum voltage distortion of 2.1%, which lies within the approved limits of IEEE 519-2014 standard. Comparative studies of the proposed inverter are conducted with different multi-level inverter configurations. FPGA-based control of the proposed inverter reduces execution time and enhances the control performance of the inverter. Evidently, the low cost function of the proposed inverter indicates the economic feasibility of the developed inverter for low-power, low-cost applications.

Investigation of level doubling network (LDN) integrated three-phase cascaded H-bridge (CHB) MLI configuration

This paper proposed a modular three-phase multilevel inverter configuration using level doubling network (LDN). This configuration doubles voltage levels in each phase, preserving modularity and without increasing the device count and ratings. Preserved modularity and switching redundancies of the configuration support inverter fault-tolerant ability. A simple control algorithm imposing a popular level-shifted carrier arrangement is used to implement the proposed configuration. Performance of the proposed configuration and PWM is analyzed and validated for multiple case studies in the Simulink environment using MATLAB.

Investigation of fault-tolerant capabilities of some recent multilevel inverter topologies

ABSTRACT In this paper, some recently proposed multilevel power converters are investigated for their fault-tolerant capabilities and improved reliability. These reported topologies are generally reduced device multilevel inverter (RD-MLIs) configurations that cannot tolerate switch failures due to absence of redundant states. Present work therefore aims to incorporate open-circuit fault-tolerant capability by adding few redundant states in switching sequences of existing topologies. The work in this paper objectively presents two existing topologies of five-level and seven-level Multi-Level Inverters (MLIs) modified for fault-tolerant (FT) capability against single switch open-circuit (OC) faults. The modification for fault-tolerant feature (FT-MLI) has intrinsic self-voltage balancing capability, low cost and control simplicity. The modified FT-MLI uses multi-carrier sinusoidal pulse-width modulation (SPWM) technique to generate control switching pulses as per desired switching sequences. Simulation and experimental results of these modified FT-MLI topologies under healthy, faulty and post-fault mode are presented and discussed. Experimental results verify the feasibility and effectiveness of these modified FT-MLI topologies which are suitable for safety-critical applications.

A Switched-DC Source Sub-Module Multilevel Inverter Topology for Renewable Energy Source Applications

This article presents a sub-module topology for switched DC source cascaded multilevel inverter configurations that require fewer switching devices and can generate a high number of voltage levels that are suitable for renewable energy sources. The proposed sub-module topology comprises eight semiconductor switches and four DC voltage sources that generate fifteen voltage levels. Furthermore, the cascaded topology is presented to increase the output voltage levels and to minimize the number of components. The proposed sub-module inverter and its cascaded topology are compared with several multilevel inverters to indicate the advantages and drawbacks of the proposal. The comparison studies show that the proposed topologies require fewer switching devices and gate drivers in comparison with other multilevel inverter topologies. In addition, the proposed cascaded topology reduces the cost of the inverter when compared to other multilevel inverter configurations. Furthermore, the power loss calculations and the implementation of the proposed topology in grid-connected photovoltaic applications are simulated and analyzed. Finally, the performance of the proposal is verified by simulation and experimental results for both symmetric and asymmetric sub-module topologies as well as for the proposed cascaded topology.

An Improved Low Switching Frequency Modulation Scheme for a Symmetric CCS-Multilevel Inverter

In this paper, a low switching frequency modulation scheme is proposed for the symmetrical configuration of cross-connected sources-based multilevel inverter (CCS-MLI). The proposed scheme, named modified nearest level modulation (mNLM), is an improvement over the conventional nearest level modulation (NLM) scheme for MLI. The implementation of mNLM, compared to the NLM, has shown a considerable reduction in total harmonic distortion (THD) at the ac output of MLI. The mNLM works through variations in the switching angles of the MLI. By suitably varying the switching angles, the THD content is brought to the minimum. An algorithm for the same is also proposed which enables the mNLM to be implemented on other MLI topologies. Simulation is carried out in MATLAB/Simulink environment and it is also extended to a hardware prototype. The effectiveness of the proposed modulation scheme is also seen in terms of improved inverter parameters such as rms voltage, rms current and generated power.

Reduced Switch Multilevel Inverter Topologies for Renewable Energy Sources

This article proposes two generalized multilevel inverter configurations that reduce the number of switching devices, isolated DC sources, and total standing voltage on power switches, making them suitable for renewable energy sources. The main topology is a multilevel inverter that handles two isolated DC sources by ten power switches to create twenty-five voltage levels. Based on the proposed main topology two generalized multilevel inverters are introduced to indicate flexibility in designing and also to minimize the number of elements. The optimal topologies for both extensive multilevel inverters are derived from different design objectives such as minimizing the number of elements (gate drivers, DC sources), achieving a large number of levels, and minimizing the total standing voltage. The main advantages of proposed topologies are a reduced number of elements than other multilevel inverters based on the comparison studies which is performed among the proposed topologies and other topologies. The power loss analysis and standalone PV application of the proposed topologies are discussed. The experimental results are presented for the proposed topology to demonstrate the correct operation of the proposal.

A novel five-level neutral-point-clamped inverter with an auxiliary DC source

Multi-level inverters have drawn much intention from researchers and industry, in which 3-level inverters have been widely used in practice. One of the most interesting issues is to increase the number of levels to achieve higher performances such as large power, high voltage and low harmonic distortion. Basic multilevel inverter configurations such as neutral point clamping diodes, flying capacitor clamping, and cascaded inverters have their own disadvantages when increasing the number of levels. To overcome these problems, different hybrid multilevel inverters have been proposed. As results, there are a lot of five-level hybrid inverters designed for practical applications. This paper proposes a new hybrid 5-level neutral point clamped inverter by adding auxiliary DC source. The novel hybrid inverter shows its performances comparable to the ideal NPC inverter fed by 4 ideal DC sources, and requires hardware simpler than cascaded and flying multilevel inverters. It has a good ability of self-balancing of the voltages across the DC capacitors. Consequently, simple and effective PWM control strategies can be utilized that enables achieving high working performances. The paper content consists of analyzing of the proposed hybrid inverter configuration, investigating the voltage balance on the DC capacitors, validating control characteristics and studying output performance when applying the carrier based pulse width modulation control. The analysis and characteristics of the proposed configuration are verified through simulation results using MATLAB/SIMULINK.

A Simple Space Vector Modulation Method With DC-Link Voltage Balancing and Reduced Common-Mode Voltage Strategy for a Three-Level T-Type Quasi-Z Source Inverter

Single-stage converters based on an impedance source (IS) network merged with a multilevel inverter remain a trending research topic, from both the topological and control perspectives, because of their potential in applications involving renewable energy. This paper presents a new, simplified space vector pulse-width modulation (SVPWM) for a three-phase three-level T-type quasi-impedance source inverter (3L-T-type qZSI). The benefits of the proposed modulation strategy include functionalities, such as boosting the input voltage and controlling the neutral-point (NP) voltage using the redundant small vectors, to mitigate the inner capacitors voltages imbalance. The proposed SVPWM guarantees a minimum common-mode voltage while preserving a very simple implementation, thus reducing the complex computations and cascaded proportional-integral (PI) control loops of the conventional SVPWM methods. The proposed algorithm can be applied to different multilevel inverter configurations combined with an IS network. A comprehensive simulation study and experimental results demonstrated the good performance of the proposed control method for dynamic response and imbalance conditions.

A novel design and performance improvement of symmetric multilevel inverter with reduced switches using genetic algorithm

Multilevel inverter (MLI) synthesizes the preferred level of alternating voltage from multiple input sources of lower-level direct voltage. By adopting a suitable harmonic elimination technique, the MLI produces stepped sinusoidal waveforms with reduced total harmonic distortion (THD) without using any filter-based applications. MLI will be an apt choice for industries operating under medium- and high-power alternating current (AC) drives, and this finds application in interfacing non-conventional energy sources with power grid lines. This paper emphasizes a novel design of performance-enhanced cascaded MLI (PEC-MLI) with less quantity of switching devices for renewable energy system. The desired switching of MLI cost function is calculated using Genetic Algorithm (GA), and the appraised firing angle is calculated and the same is given as input to the Pulse Width Modulation (PWM) technique coded with chosen Nearest Voltage Level (NVL) control scheme. The gating signals generated for switching devices with the control strategies of NVL—PWM and hybrid PWM techniques using Genetic Algorithm. The MATLAB/Simulink model successfully evaluates the performance of proposed MLI. The simulated results analyze the system efficiency by comparing it with other similar MLI configuration cited in recent research articles. An effective realization of proposed MLI is experimented successfully and whose results are found be satisfactory with the simulated results.

E K θ multilevel inverter – a minimal switch novel configuration for higher number of output voltage levels

In this study, a new multilevel inverter (MLI) configuration is proposed to generate higher number of levels with minimal control switches. The proposed inverter's nomenclature is EK θ MLI, termed from its stems of shape. Conventional single-phase H-bridge module is modified to design the structure of θ MLI called ‘θ cell’ (where, K = 0) by incorporating three symmetrical DC-sources and replacing one leg of H-bridge by bidirectional switches. The θ cell of the proposed EK θ MLI generates five-level AC waveform at the output by using only four controlled switches (two unidirectional and two bidirectional). Therefore, the size, cost and switching logic of the MLI is reduced. The basic structure of EK θ MLI called ‘Eθ MLI’ (where K = 1) is designed which is capable of generating seven-level. For further extension, double-switch-E cell (DS-E cell) is added in the middle and each DS-E cell increases the four levels by utilising two bidirectional switches and two DC supplies. The generalised MLI configuration is explained in niceties to generate a higher number of levels (more than 5). The modes of operation, voltage across the switches, power losses of EK θ are discussed. The proposed MLI is experimentally investigated using level shifting pulse width modulation.

Comparative Analysis of Two-Level and Multi-Level Inverter Configuration

Comparative Analysis of Two-Level and Multi-Level Inverter Configuration

Five‐level one‐capacitor boost multilevel inverter

Multilevel inverter configurations are a suitable candidate for medium and high power applications. This study presents a new one-capacitor-based five-level (2 V dc , V dc , 0, − V dc , − 2 V dc ) boost multilevel inverter. The single-phase version of the proposed formation has one dc-source, eight switches and one capacitor. To provide boosting ability, the inverter is operating based on charge-pump theory, where the capacitor is charging in parallel and discharging in series connections to provide a higher output voltage. The proposed configuration requires simple control tasks, and for this purpose, level-shift pulse width modulation strategy, where the reference signal is compared with four carriers, is implemented to drive the switches and generates the required pulses pattern. The developed inverter has some distinct features like the usage of only one dc-source and one-capacitor, compact size, simple control requirements and boosting ability. The system is simulated with MATLAB/Simulink and a hardware prototype is developed to verify the performance of the developed five-level configuration. The results show that the developed five-level multilevel inverter reaches the expected performance

Review of Multilevel Inverters and Their Control Techniques

Multi-level inverter is attaining higher AC power using a series of power semiconductor switches with numerous lower voltage DC sources to implement the power conversion by synthesizing a staircase voltage waveform. Sources like super capacitors, batteries, solar panels and other renewable energy voltage sources make up the multiple DC voltage sources. This work looks at the advantages and likely disadvantage of multi-level inverter, highlighting some of the shortfalls of existing inverter topologies while considering the effects of emerging Hybrid MLI Topologies. Hence this review paper proposes a distinctive seven level cascaded H-bridge multi-level inverter configuration in which the POD PWM technique is adopted. This design would potentially redress the problems inherent in other inverter circuit topologies reviewed.

Review of Multilevel Inverters and Their Control Techniques

Multi-level inverter is attaining higher AC power using a series of power semiconductor switches with numerous lower voltage DC sources to implement the power conversion by synthesizing a staircase voltage waveform. Sources like super capacitors, batteries, solar panels and other renewable energy voltage sources make up the multiple DC voltage sources. This work looks at the advantages and likely disadvantage of multi-level inverter, highlighting some of the shortfalls of existing inverter topologies while considering the effects of emerging Hybrid MLI Topologies. Hence this review paper proposes a distinctive seven level cascaded H-bridge multi-level inverter configuration in which the POD PWM technique is adopted. This design would potentially redress the problems inherent in other inverter circuit topologies reviewed.

Unified Power Quality Conditioner using PV Fed SVPWM based Multilevel Converters for Power Quality Improvement

This paper presents a solar photovoltaic based unified power quality conditioner (PV-UPQC). The proposed system consists of a shunt compensator (ShC), series compensator (SeC) and PV array connected in parallel to a common dc-link. A three-level diode clamped multilevel inverter configuration is used as shunt and series converters. The SVPWM technique provides reduction in the common mode voltage and the balancing of the dc link voltage. The shunt compensation converter extracts power from PV array and provides compensation for load harmonic currents. The series compensation converter compensates for the power quality (PQ) problems such as grid voltage sags/swells and source harmonic voltages. The proposed system utilizes space vector pulse width modulation (SV-PWM) in multilevel converter topology for the mitigating the power quality problems using PV-UPQC. The proposed system improves PQ and also utilize RES, it also simultaneously improves both current and voltage disturbances. The performance of the system is analyzed in MATLAB/Simulink for nonlinear load conditions.

Phase Reconfiguring Technique for Enhancing the Modulation Index of Multilevel Inverter Fed Nine-Phase IM Drive

In this article, a multilevel inverter (MLI) scheme is proposed for four-pole (4-pole), nine-phase (9-phase) induction motor (IM) drives with improved dc bus utilization as well as reduced device count. The proposed MLI is realized with nine three-switch inverter legs (3-SIL) and a single dc source. In the proposed MLI, each 3-SIL is utilized for exciting the two identical voltage profile coils/phase of the four-pole (4-pole) stator winding, which means each leg has to be modulated with two references. These two independent references/leg will limit the modulation index (M.I) of 3-SIL-based proposed MLI. This lower M.I will result in a requirement of the higher magnitude of dc-link voltage to achieve the rated load voltage requirement. In this article, an effective phase reconfiguring concept is proposed for reducing the dc-link voltage requirement of the proposed MLI. In addition, all the possibilities of phase reconfiguring details for proposed MLI-fed 9-phase IM drive are also presented. A three-phase carrier-based space vector pulsewidth modulation is implemented for improving the linear modulation range of proposed MLI configuration further. In contrast with existing 9-phase three-level inverters, like NPC and FC, the proposed MLI configuration requires only one dc link (with half of the magnitude) and lesser number of semiconductor devices. The proposed MLI-fed, 5 hp, 9-phase, 4-pole IM drive is validated by using Ansys Maxwell FEM simulation and experimental prototype for entire modulation range.

A Hybrid Multilevel Inverter Scheme for Nine-Phase PPMIM Drive by Using Three-Phase Five-Leg Inverters

In pole-phase modulation, the phase order is coming down by pole ratio times in high pole mode, which results in the higher magnitude of spatial harmonics as well as higher torque ripple. In this article, the available three identical voltage-fed windings per effective phase in three-phase 12-pole (3PH-12PO) mode are used to develop the simple multilevel inverter (MLI) configuration for minimizing torque ripple. The proposed MLI scheme is realized with three five-leg inverter modules. Each five-leg inverter module will generate three-level voltage across the phase, thereby resultant voltage seen by each phase winding is five-level voltage in 3PH-12PO mode. This multilevel voltage will improve the torque ripple profile of the motor drive. In addition, the proposed MLI scheme along with phase grouping will enrich the linear modulation range of the pole-phase-modulated induction motor (PPMIM) drive in nine-phase four-pole (9PH-4PO) mode. The switches used to generate a multilevel voltage in 3PH-12PO mode are effectively utilized for blocking the flow of circulating currents. As compared with other conventional nine-phase five-level inverters the proposed five-level inverter requires only 30 switches and it does not require extra clamping diodes/capacitors and extra bidirectional switches for isolating neutrals in 9PH-4PO operation. The validation of proposed MLI scheme is done on a 5-hp nine-phase IM with Ansys Maxwell as well as laboratory prototype for entire modulation range using V/f = constant control.

Harmonic Elimination of a PV Based Cascaded H-bridge Seven Level Inverter for Induction Motor Drive

In today’s era, reliable and good quality power is an essential requirement in industry, which can be supplied by inverters at medium and high power. Most of the appliances in the industry require high power or medium power for their operation. Power electronics devices such as inverters work on medium voltage and high power and are suitable for industrial applications and renewable particularly Photovoltaic (PV) integration. Multilevel inverters are more superior to conventional inverters because of lower harmonics and switching losses, but as the number of levels increases, complexity also increases. Therefore, maintaining the harmonics at lower level and lesser complexity of multilevel inverters is a challenge for researchers. In this research paper, a novel approach for implementation of seven level cascaded H- bridge configuration of multilevel inverter using direct current source and photovoltaic panels has been demonstrated. The basic working principle of seven level cascaded hybrid bridge inverter, pulse width modulation techniques and total harmonic distortion are explained through simulations in Matlab and Xilinx 14.3 software and the same is experimentally validated through FPGA controller based Spartan 6. The designed seven level inverter results in lower total harmonic distortion with lesser complexity when used to connect PV panels.

Reduction of Current Harmonics by Cascaded Multilevel Inverter based Shunt Active Power Filters

Majority of loads in use today are power electronics based non-linear devices. Despite being compact and providing low energy consumption these loads generate inherent harmonics. Harmonics have several adverse effects such as interference with the communication lines, incorrect meter readings, increased losses, increased heating of electrical and sensitive electronic equipment. Sophisticated power electronic converter based filters named as Shunt Active Power Filters (SAPF) are widely being employed that provide superior harmonic filtering capabilities. Basic objective of SAPF is to generate or absorb currents that compensate harmonic currents produced by non- linear loads. These currents should be opposite in phase but have equivalent magnitude as that of harmonic currents. As compared to Diode-Clamped and Flying capacitor multilevel inverters, Cascaded multilevel configuration is employed for many applications due to ease of control and simple structure. In this research paper, power quality in a three-phase three- wire system is improved by reducing source side current harmonics produced by a non-linear load. Initially a three-level Cascaded multilevel inverter based SAPF is developed and its performance is analyzed by using advanced Adaptive Neuro Fuzzy Inference System (ANFIS) controller. DC link capacitor voltage and percentage Total Harmonic Distortion (%THD) in source currents is measured at PCC for balanced loading conditions and results are compared. In this paper, it is also proposed to incorporate multilevel inverter topology concepts by employing Five-Level and Seven-Level Cascaded Multilevel Inverters as VSI circuit for SAPF. Performance of these multilevel Shunt Active power filters is analyzed by ANFIS controller. Instantaneous Active-Reactive power theory is implemented to compute reference compensating currents for all Shunt Active power filter models. Phase Disposition type Pulse Width modulation is chosen for generating gate pulses for VSI circuits of all Cascaded multilevel inverter configurations. Three-level, Five-level and Seven-level Shunt active power filter models are developed and simulated using MATLAB/ Simulink and results are presented.