Multilevel Flash Memory Research Articles

Performance Analysis of Concatenated Coding to Increase the Endurance of Multilevel NAND Flash Memory

The increasing storage density of modern NAND flash memory chips, achieved both due to scaling down the cell size, and due to the increasing number of used cell states, leads to a decrease in data storage reliability, namely, error probability, endurance (number of P/E cycling) and retention time. Error correction codes are often used to improve the reliability of data storage in multilevel flash memory. The effectiveness of using error correction codes is largely determined by the model accuracy that exhibits the basic processes associated with writing and reading data. The paper describes the main sources of disturbances for a flash cell that affect the threshold voltage of the cell in NAND flash memory, and represents an explicit form of the threshold voltage distribution. As an approximation of the obtained threshold voltage distribution, a Normal-Laplace mixture model was shown to be a good fit in multilevel flash memories for a large number of rewriting cycles. For this model, a performance analysis of the concatenated coding scheme with an outer Reed-Solomon code and an inner multilevel code consisting of binary component codes is carried out. The performed analysis makes it possible to obtain tradeoffs between the error probability, storage density, and the number of P/E cycling. The resulting tradeoffs show that the considered concatenated coding schemes allow, due to a very slight decrease in the storage density, to increase the number of P/E cycling up to 2–2.5 times than their nominal endurance specification while maintaining the required value of the bit error probability.

Latency optimized clustered error mitigation for multi-level flash memory using product code

Soft errors due to radiation-induced multi-bit upsets (MBUs) are very prominent in the present flash memories built with ultra large scale VLSI technology. Use of multi-level cells in flash memories increase the chance of adjacent MBUs or clustered error. Single bit error detection and correction (EDAC) codes are not enough to mitigate the effect of clustered error due to their small error correction capability. On the other hand, commonly used multi-bit EDAC codes have large overhead, complex decoding circuitry, high error correction latency and are unable to correct large number adjacent erroneous bits. In this paper, we have proposed a product code coined as linear shortened block code based product code (LSBCPC) for mitigation of clustered error in the flash memory devices. LSBCPC utilizes latency optimized scalable shortened block code as the component code and can correct higher number of adjacent erroneous bits in memory devices compared to the other state of the art solutions. The proposed LSBCPC promises better error correction coverage with 28%, 14%, and 13% reduction in terms of redundant bits, 13%, 11%, and 10% reduction in terms of area and 24%, 26%,and 22% reduction in terms of latency in 16 × 16, 32 × 32 and 64 × 64 memory devices respectively compared to the highly cited research work. The performance of the proposed method is validated in terms of redundant bits, error correction coverage, mean error to failure, area consumption, power utilization and decoding latency.

Multi-level flash memory device based on stacked anisotropic ReS2-boron nitride-graphene heterostructures.

Charge-trapping memory devices based on two-dimensional (2D) material heterostructures possess an atomically thin structure and excellent charge transport capability, making them promising candidates for next-generation flash memories to achieve miniaturized size, high storage capacity, fast switch speed, and low power consumption. Here, we report a nonvolatile floating-gate memory device based on an ReS2/boron nitride/graphene heterostructure. The implemented ReS2 memory device displays a large memory window exceeding 100 V, leading to an ultrahigh current ratio over 108 between programming and erasing states. The ReS2 memory device also exhibits an ultrafast switch speed of 1 μs. In addition, the device can endure hundreds of switching cycles and shows stable retention characteristics with ∼40% charge remaining after 10 years. More importantly, taking advantage of its anisotropic electrical properties, a single ReS2 flake can achieve direction-sensitive multi-level data storage to enhance the data storage density. On the basis of these characteristics, the proposed ReS2 memory device is potentially able to serve the entire memory device hierarchy, meeting the need for scalability, capacity, speed, retention, and endurance at each level.

Concatenated Coding for Multilevel Flash Memory with Low Error Correction Capabilities in Outer Stage

One of the approaches to organization of error correcting coding for multilevel flash memory is based on concatenated construction, in particular, on multidimensional lattices for inner coding. A characteristic feature of such structures is the dominance of the complexity of the outer decoder in the total decoder complexity. Therefore the concatenated construction with low-complexity outer decoder may be attractive since in practical applications the decoder complexity is the crucial limitation for the usage of the error correction coding.
 We consider a concatenated coding scheme for multilevel flash memory with the Barnes-Wall lattice based codes as an inner code and the Reed-Solomon code with correction up to 4…5 errors as an outer one.
 Performance analysis is fulfilled for a model characterizing the basic physical features of a flash memory cell with non-uniform target voltage levels and noise variance dependent on the recorded value (input-dependent additive Gaussian noise, ID-AGN). For this model we develop a modification of our approach for evaluation the error probability for the inner code. This modification uses the parallel structure of the inner code trellis which significantly reduces the computational complexity of the performance estimation. We present numerical examples of achievable recording density for the Reed-Solomon codes with correction up to four errors as the outer code for wide range of the retention time and number of write/read cycles.

Union Bound Analysis and Code Design for Multilevel Flash Memory Channels

Multilevel flash memories enable multiple bits to be stored in a single memory cell and hence a significant increase of the storage capacity. The multiple bits that are used for labeling the threshold voltage level of a memory cell belong to different pages. A multilevel flash memory channel resembles a multi-user channel with asymmetric noise, while the data of different pages, which are encoded independently, resembles data of multiple users. In this paper, performance analyses are proposed for this channel by using the union bound technique. In particular, we investigated two different binary labeling schemes of a cell level, the Gray labeling and non-Gray labeling with three maximum-likelihood (ML)-based decoding schemes, which are the joint multi-page ML decoding, page-separate ML decoding, and default setting ML decoding. Our analysis reveals an asymptotic diminishing rate of decoding errors as the channel noise approaches zero, based on which the code design criteria are proposed. It is shown theoretically that the Gray mapping has no joint (i.e., multi-page) decoding gain. The corresponding diminishing decoding error rate is dominated by the weakest code in each page and hence a separate decoding scheme is adequate. On the other hand, the non-Gray mapping has a joint decoding gain which means the weak code can exploit the decoding of the strong code and the diminishing rate of its decoding errors is not subject to the cask effect. Therefore, for Gray mapping, a symmetric coding scheme using equal-strength code for each page achieves better error performance, while for non-Gray mapping with joint decoding, the symmetric coding is not necessary. Moreover, by using the asymmetric coding scheme through assigning different code rates to different pages, the non-Gray mapping can achieve higher overall sum rate than Gray mapping with a similar decoding error rate performance.

Diversity Combining Type I-Hybrid ARQ protocol over m-ary Asymmetric Varshamov channels

Errors in multilevel flash memories and multilevel optical systems are asymmetric in nature because of the underlying device physics. These errors can be modeled using the m-ary asymmetric channel. In this work, a general m( ≥ 2)-ary Asymmetric Varshamov (AV) channel for these systems is introduced. Also, a Divesting Combining Type-I Hybrid ARQ protocol using t-Asymmetric Error Correcting/All Asymmetric Error Detecting (t-AEC/AAED) codes is presented and its throughput performance is studied.

Codes correcting restricted errors

We study the largest possible length B of $$(B-1)$$ -dimensional linear codes over $$\mathbb {F}_q$$ which can correct up to t errors taken from a restricted set $${\mathcal {A}}\subseteq \mathbb {F}_q^*$$ . Such codes can be applied to multilevel flash memories. Moreover, in the case that $$q=p$$ is a prime and the errors are limited by a constant we show that often the primitive $$\ell $$ th roots of unity, where $$\ell $$ is a prime divisor of $$p-1$$ , define good such codes.

Gray codes over certain run-length sequences for local rank modulation

In the local rank modulation (LRM) scheme, a sliding window produces a sequence of permutations by moving over a sequence of variables. LRM has been presented as a method of storing data in flash memory, which represents a natural generalization of the classical rank modulation scheme. In this paper, we present a study on Gray codes over certain run-length sequences for the $(1,2,n)$-LRM scheme to simulate virtual multilevel flash memory cells while maintaining the advantages of LRM. Unlike previous studies on the LRM scheme, we present Gray codes over certain run-length sequences in the $(1,2,n)$-LRM scheme. This class of Gray codes can overcome the drawback of the many distinct charge levels required in the rank modulation scheme and in certain Gray codes for LRM. Furthermore, we demonstrate that the proposed codes have an asymptotically optimal rate.

Enhancing the Expected Lifetime of NAND Flash by Short <inline-formula> <tex-math notation="LaTeX">$q$ </tex-math> </inline-formula>-Ary WOM Codes

Write-once memory (WOM) codes can be used to enhance the lifetime of multi-level flash memories by constraining unidirectional changes of cell levels. A $q$ -ary WOM code on integer lattices can be defined by a message decoding function and an updating function. Instead of focusing on the worst-case performance, i.e., the guaranteed number of writes of WOM codes, we study the average number of writes that can be successfully performed, assuming that the input alphabet is the same on each write. We model the updating of messages in a WOM as a Markov process on lattices, and present techniques to evaluate the average number of writes. Several code constructions are compared. A greedy algorithm is presented to obtain the optimal updating function of a given decoding function.

Concatenated Reed–Solomon/Lattice Coding for Multilevel Flash Memory

The article considers concatenated coding scheme for multilevel flash memory. In this scheme the inner stage is a finite subset of a multidimensional lattice (lattice code) and the outer stage uses Reed–Solomon code. Performance analysis is done for a model characterizing the basic physical features of a flash memory cell with non-uniform target voltage levels and noise variance dependent on the recorded value (input-dependent additive Gaussian noise, ID-AGN). For this model we develop a new approach to evaluating the error probability for the inner code. This approach is based on one-dimensional numerical integration of product of the characteristic functions of random variables used in the decoding process. It is shown how the parameters of the concatenated coding scheme can be adapted to keep the required error probability when the retention period and/or number of program-erasure cycles increase.

Low Read Latency Rewriting Codes for Multi-Level 3-D NAND Flash

Rewriting codes can improve the lifetime capacity of NAND flash. All existing $q$ -ary rewriting codes for NAND flash assume that the exact cell levels are known to decoders, and thus the number of reads needed is $q-1$ , while the current NAND technology enables low latency page reads by dividing a physical page into $\log q$ logical pages, so that the average number of reads per page is $\frac {q-1}{\log q}$ . We consider 2-write rewriting codes that enable low latency page reads for multi-level NAND flash memories. We design a low read latency rewriting code that enables 17% capacity improvement and maintains 1.5 reads per page for four-level multiple-level cells. We also design codes for eight-level triple level cells that enable 11% and 24% capacity improvement with 2 and 2.5 reads per page, respectively. The same Gray codes in current NAND technology that map binary data to physical cell levels are applied to avoid redesigning hardware and circuits inside the chip.

Construction of Parallel Random I/O Codes Using Coset Coding with Hamming Codes

Random input/output (RIO) code is a coding scheme that enables reading of one logical page using a single read threshold in multilevel flash memory. The construction of RIO codes is equivalent to the construction of WOM codes. Parallel RIO (P-RIO) code is an RIO code that encodes all pages in parallel. In this paper, we utilize coset coding with Hamming codes in order to construct P-RIO codes. Coset coding is a technique that constructs WOM codes using linear binary codes. We leverage the information on the data of all pages to encode each page. Our constructed codes store more pages than RIO codes constructed via coset coding.

Capacity of Multilevel NAND Flash Memory Channels

In this paper, we initiate a first information-theoretic study on multilevel NAND flash memory channels with intercell interference. More specifically, for a multilevel NAND flash memory channel under mild assumptions, we first prove that such a channel is indecomposable and it features asymptotic equipartition property; we then further prove that stationary processes achieve its information capacity, and consequently, as the order tends to infinity, its Markov capacity converges to its information capacity; eventually, we establish that its operational capacity is equal to its information capacity. Our results suggest that it is highly plausible to apply the ideas and techniques in the computation of the capacity of finite-state channels, which are relatively better explored, to that of the capacity of multilevel NAND flash memory channels.

Dummy Read Scheme for Lifetime Improvement of MLC NAND Flash Memories

Program/erase cycling endurance is one of the most critical reliability challenges for multi-level NAND flash memories. Deliberately designed delay between cycles is found to extend the endurance of nanoscale NAND flash memory cells. In addition, the effect of chip temperature is extensively investigated. A new dummy read operation scheme is proposed to further enhance cell reliability by effectively suppressing cycling-induced error bits in gigabit memory arrays.

Random telegraph noise on the threshold voltage of multi-level flash memory☆☆Project supported by the National Research Program of China (Grant No. 2016YFB0400402), the Natural Science Foundation of Jiangsu Province, China (Grant No. BK20141321), and the National Natural Science Foundation of China (Grant No. 61627804).

We investigate the impact of random telegraph noise (RTN) on the threshold voltage of multi-level NOR flash memory. It is found that the threshold voltage variation () and the distribution due to RTN increase with the programmed level () of flash cells. The gate voltage dependence of RTN amplitude and the variability of RTN time constants suggest that the large RTN amplitude and distribution at the high program level is attributed to the charge trapping in the tunneling oxide layer induced by the high programming voltages. A three-dimensional TCAD simulation based on a percolation path model further reveals the contribution of those trapped charges to the threshold voltage variation and distribution in flash memory.

Performance of Multilevel Flash Memories With Different Binary Labelings: A Multi-User Perspective

In this paper, we study the performance of different decoding schemes for multilevel flash memories where each page in every block is encoded independently. We focus on multi-level cell flash memory, which is modeled as a two-user multiple-access channel suffering from asymmetric noise. The uniform rate regions and sum rates of treating interference as noise decoding and successive cancelation decoding are investigated for a program/erase cycling model and a data retention model. We examine the effect of different binary labelings of the cell levels, as well as the impact of further quantization of the memory output (i.e., additional read thresholds). Finally, we extend our analysis to the three-level cell flash memory.

Detector for MLC NAND Flash Memory Using Neighbor-<italic>A-Priori</italic> Information

Cell-to-cell interference (CCI), arising from parasitic coupling-capacitance between adjacent cells, is a major factor for the degradation of cell threshold voltage in today’s flash memory chips. In this paper, three novel postprocessing detection schemes that exploit the a priori information of neighboring/interfering cells for mitigating the CCI effect in multilevel cell NAND flash memory are presented. The proposed schemes are referred to as the Even- A-Priori (Even-AP), the All- A-Priori (All-AP), and the All-AP-coupling-capacitance ratio (CCR) detectors. The main idea is to remove the CCI component from the interfering cells before CCI cancellation from the victim cell. Specifically, the mean CCRs along the victim cell’s vertical and diagonal directions are estimated to enable more accurate CCI cancellation. Performance analysis and simulation results show that the channel signal-to-noise ratio performance can be improved by up to 2 dB at a cell storage capacity of 1.8 bits/cell, which is significantly improved compared with some prior-art detection schemes.

Polar Code Design for Noisy Blackwell Channels

In this letter, we introduce a class of discrete memoryless broadcast channels, called noisy Blackwell channels, which generalize the Blackwell channel to include noise and to more than two users. We design the polar code for the noisy Blackwell channel based on Marton’s coding scheme. We choose auxiliary random variables and the mapping from auxiliary random variables to the channel input, such that the sum-rate capacity can be achieved very closely. Furthermore, we show that the designed polar code can be applied to multi-level cell flash memories for improving random I/O performance. The simulation results demonstrate that our designed polar codes achieve good performance even for a large number of users.

New Results on Codes Correcting Single Error of Limited Magnitude for Flash Memory

Some physical effects that limit the reliability and performance of multilevel flash memories induce errors that have low magnitudes and are dominantly asymmetric. This motivated the application of the asymmetric limited magnitude error model in flash memory. In this paper, we present a new construction of quasi-perfect codes for such errors, and we also study the perfect codes with symmetric errors. Moreover, we show some nonexistence results on perfect codes for correcting single error of limited magnitude.

Cyclopentadithiophene based branched polymer electrets synthesized by friedel–crafts polymerization

ABSTRACTIn this report, the BF3·Et2O catalyzed Friedel–Crafts polymerization of cyclopentadithiophene monomers for branched conjugation‐interrupted polymer electrets with the potential application in OFET memories were demonstrated. Branched polycyclopentadithiophenes with controlled molecular weights (Mn) of approximately 8800 g/mol and narrow polydispersity index (PDI = 1.08–1.49) were obtained through the optimized polymerization temperature and time, and monomer addition strategy. OFET memories by using the synthesized polymers as the electret layers were fabricated and exhibited multilevel flash memory behaviors, wide memory windows, high on/off ratios, and long retention lifetime. Impressively, due to the strong hydrophobic, extended pi‐conjugation and electron‐donating properties, the branched polycyclopentadithiophene based OFET memory exhibited much lower programming voltage than other branched polymer electrets based devices. It is expected that the branched polycyclopentadithiophenes probably have potential application in other organic electronic devices. © 2016 Wiley Periodicals, Inc. J. Polym. Sci., Part A: Polym. Chem. 2016, 54, 3140–3150