multi-DSP System Research Articles

Zeroing for HW-efficient compressed sensing architectures targeting data compression in wireless sensor networks

The design of ultra-low cost wireless body sensor networks for wearable biomedical monitors has been made possible by today technology scaling. In these systems, a typically multi-channel biosignal sensor takes care of the operations of acquisition, data compression and final output transmission or storage. Furthermore, since these sensors are usually battery powered, the achievement of minimal energy operation is a fundamental issue. To this aim, several aspects must be considered, ranging from signal processing to architectural optimization. In this paper we consider the recently proposed rakeness-based compressed sensing (CS) paradigm along with its zeroing companion. With respect to a standard CS base sensor, the first approach allows us to further increase compression rate without sensible signal quality degradation by exploiting localization of input signal energy. The latter paradigm is here formalized and applied to further reduce the energy consumption of the sensing node. The application of both rakeness and zeroing allows for trading off energy from the compression stage to the transmission or storage one. Different cases are taken into account, by considering a realistic model of an ultra-low-power multicore DSP system.

Guest Editorial: Multi-Core Embedded Computing for Signal Processing

Embedded systems with multi-core designs are becoming increasingly important for signal processing in recent years. While embedded multi-core system design can significantly improve efficiency for signal processing systems, several critical issues from the hardware and software perspectives of embedded multi-core systems need to be carefully designed for different applications in signal processing. Some of the most important issues are the hardware architecture design, software tools, programming models, and algorithm parallelization for embedded multi-core computing. Usually, the system optimization for the above issues is closely related to the targeted application domain. This special issue focuses on the latest development and technical solutions concerning the multi-core embedded computing for signal processing from the hardware and software perspectives. This special issue consists of six papers related to the multicore embedded computing for signal processing systems. They can be partitioned into three categories: hardware architecture design, system and programming tools, and application-specific algorithm parallelization. Firstly, the paper “EVE: A Flexible SIMD Coprocessor for Embedded Vision Applications”, by Sankaran et al., is focused on the hardware architecture design for embedded vision applications. In this paper, they present a flexible SIMD architecture that is optimized for embedded vision applications. The proposed embedded vision co-processor is efficient in power and area consumption, and it can accelerate many low-level and mid-level vision tasks. There are three papers related to the system and programming tools for multi-core embedded computing in this special issue. For the paper titled “C++ Support and Applications for Embedded Multicore DSP Systems”, authored by Kuan et al., they propose a layered design to provide a code size aware C++ library support. This work provides C++ programming support to enhance low-level programming APIs that can be used to exploit DSPs, SIMD instructions, and DMAs on embedded multicore systems. They evaluate their C++ support with image blurring and JPEG compression tasks and show significant computational speed-up. Moreover, the paper “Message-Passing Programming for Embedded Multicore Signal-Processing Platforms”, by Hung et al., presents a light-weight MPI-like message-passing library with a three-layer modular design, which supports message-passing on several popular embedded multi-core signal-processing platforms. In this paper, they present a message-passing library for inter-core communications on different multi-core computing platforms to provide a standard, portable and efficient message-passing library for embedded multicore platforms. For the third paper in the category of system and programming tools, “Design Issues in a Performance Monitor for Multi-core Embedded Systems”, authored by Lin et al., presents a multi-core performance monitor and they evaluate the effects of monitor overheads for difference types of tasks, including CPU-bound and IO-bound tasks. This paper proposes an adaptive performance monitoring mechanism to reduce the impact of the monitoring overhead on the application, without sacrificing accuracy or immediacy of the monitored information. They show experimental results with different monitoring periods for a digital recording system. S.<H. Lai (*) : J.<K. Lee National Tsing Hua University, Hsinchu, Taiwan e-mail: lai@cs.nthu.edu.tw

C++ Support and Applications for Embedded Multicore DSP Systems

In recent years embedded systems have entered the multicore era. As the number of cores keeps growing in embedded systems, it becomes more important to provide programming support which considers e...

Flexible DMA subsystem in multi-core platforms for video applications

We propose a flexible DMA subsystem suitable for multi-core systems, in which DMA set-up routines are separated from DMA requesting threads and DMA completion flags can quickly be checked by DMA synchronizing threads. We will briefly describe its architecture and implementation. By using a multi-core DSP system with the proposed DMA subsystem, we implemented an H.264/AVC software decoder that can decode D1 30 frames per second when the system operating clock frequency is about 265MHz, assuming that all cores are operated at the same system clock frequency. With experimental results for the H.264 decoder, we confirmed its flexibility and performance improvement.

Research on self-adaptive reconfigurable multi-DSP system in PXI platform

In this work,a new run-time reconfiguration multi-DSP system architecture was given.In this system,combining the characteristic of the multi-processor parallel computation and worm arithmetic,a mixed architecture that can be adaptively expanded based on shared bus and linkports was constructed.And the system was designed and discussed from the point of measurability.Self-Adaptive operating system,a feasible project was proposed for the high speed Self-Adaptive signal processing platform.The hardware debugging,system testing and the software loading methods were introduced.These works may offer some meaningful reference and guide for some similar systems developed in the future.

A complete compiler approach to auto-parallelizing C programs for multi-DSP systems

Auto-parallelizing compilers for embedded applications have been unsuccessful due to the widespread use of pointer arithmetic and the complex memory model of multiple-address space digital signal processors (DSPs). This work develops, for the first time, a complete auto-parallelization approach, which overcomes these issues. It first combines a pointer conversion technique with a new modulo elimination transformation for program recovery enabling later parallelization stages. Next, it integrates a novel data transformation technique that exposes the processor location of partitioned data. When this is combined with a new address resolution mechanism, it generates efficient programs that run on multiple address spaces without using message passing. Furthermore, as DSPs do not possess any data cache structure, an optimization is presented which transforms the program to both exploit remote data locality and local memory bandwidth. This parallelization approach is applied to the DSPstone and UTDSP benchmark suites, giving an average speedup of 3.78 on four analog devices TigerSHARC TS-101 processors.

A flexible DSP-based network for real-time image-processing

This paper proposed a general purpose real-time image processing system based on a flexible DSP-based Network, which is implemented by a high bandwidth communication channel, links. The links is realized using FPGA and provides a bandwidth of 12. 8 Gbit/s. Using the links, The topologic of multi-DSP system can be changed online to meet the variabilities of the parallel algorithm of image processing. The system can be assembled with utmost tens of boards and maintain the high communication speed. Analysis of the system adaptivity to image processing is testified followed by actual results.

Experimental parallel implementation of a wavelet-based still image encoder

A still image encoder implementation is presented for a multi-DSP system called PARNEU, which has previously been developed for neural network and signal processing applications. The core of the implementation is based on experimental mappings of discrete wavelet transform (DWT) on the parallel processor architecture. PARNEU has a flexible interconnection network architecture with message passing, which allows adding more processing units (PUs) to the system whenever more computational power is needed. Program code can be written to adapt to the number of PUs. This is utilized in the presented encoder implementation with emphasis on load balancing among processors as well as on balance between communication and computation. Performance of the implementation is measured with a scaleable number of processors and compared to a sequential reference implementation. Results show that the DWT phase can be efficiently parallelized on PARNEU with 95.6% of its time spent on true parallel computation. The overall speedup with four processors is 2.25, which could be improved by further optimization of an adaptive scanning phase of the encoder.

A Rapid Prototyping Environment for Multi-DSP Systems based on Accurate Performance Prediction

A Rapid Prototyping Environment for Multi-DSP Systems based on Accurate Performance Prediction

A multi-DSP system for the neutron high resolution Fourier diffractometer

The multi-DSP data acquisition system for neutron time-of-flight spectrum measurements requiring fast real-time data processing is designed and is operated at the neutron High Resolution Fourier Diffractometer (HRFD). The use of high performance DSPs and front-end electronics based on flexible PLDs allows increasing of the efficiency of neutron diffractometers with a Fourier chopper and a multi-element detector system by the method of electronic time-focusing.

ある種のマルチDSPシステムにおける多目的最適化問題に対する分枝限定法の適用

ある種のマルチDSPシステムにおける多目的最適化問題に対する分枝限定法の適用

ある種のマルチDSPシステムのスケジューリング問題に対する最適化アルゴリズム

ある種のマルチDSPシステムのスケジューリング問題に対する最適化アルゴリズム

超高真空対応磁気浮上・２軸一体形ウェーハハンドリングロボットの開発

From the viewpoint of freedom from contamination, wafer handling systems with contactless mechanisms are required in the production of VLSI. Authors have developed a clean and vacuum-compatible wafer handling robot using an electro-magnetic suspension system. This two d. o. f. (degree of freedom) wafer handring robot can be applied to a wafer-hoist, a turn-table and a swing-arm in an ultra-high vacuum. The robot controller is fully digitalized by multi-DSP system. And the following advanced control methods are implemennted: 1) Electro-magnetic suspension control by decoupling control scheme. 2) Precise positioning by sliding mode control. The decoupling control enables to hold the position of the rotational axis precisely, regardless influence of the arm position. The sliding mode control using the coarse signal (72 pulse/rev. ) of position sensor significantly improves the overshoot at the rotational positioning. These control schemes are introduced and experimental results are shown in this paper.

The ring array processor: A multiprocessing peripheral for connectionist applications

We have designed and implemented a Ring Array Processor (RAP) for fast implementation of our continuous speech recognition training algorithms, which are currently dominated by layered “neural” network calculations. The RAP is a multi-DSP system with a low-latency ring interconnection scheme using programmable gate array technology and a significant amount of local memory per node (4–16 Mbytes of dynamic memory and 256 Kbytes of fast static RAM). Theoretical peak performance is 128 MFLOPS/board. A working system with 20 nodes has been used for our research at rates of 200–300 million connections per second for probability evaluation, and at roughly 30–60 million connection updates per second for training. A fully functional system with 40 nodes has also been benchmarked at roughly twice these rates. While practical considerations such as workstation address space restrict current implementations to 64 nodes, the architecture scales to about 16,000 nodes. For problems with 2 units per processor, communication and control overhead would reduce peak performance on the error back-propagation algorithm to about 50% of a linear speedup. This report describes the motivation for the RAP and shows how the architecture matches the target algorithm. We further describe some of the key features of the hardware and software design.

A Modelbased Real-time Fault Diagnosis SystemFor Technical Processes

The aim of the project is the modelbased diagnosis of faults in production systems. We use a real-time measurement-system to get the state of the process and to react in a short time to avoid high repair costs. The behavior of the process will be simulated with different simulators. The main simulator is a petri-net simulator which calculates the behavior of the entire process. The petri-net simulator is a discret simulator and especially in case of discrepancies between the state of the petri-net simulator and the technical process, a continuous simulator is requiered. With this simulator get more information about subprocesses like a pneumatical cylinder. In order to get a high performance diagnosis-system the simulators as well as the diagnosis algorithm are distributed on a multi-transputer system. For the continuous simulator a multi-DSP system with four signalprocessors TMS320C40 is used. For the distributed diagnosis-system local experts are implemented in process-interfaces, which are located near the subprocess, and one global expert controls the overall system.