Multicore Systems Research Articles

Optimized Scheduling of Periodic Hard Real-Time Multicore Systems

Multicore systems were developed to provide a substantial performance increase over monocore systems. But shared hardware resources are a problem as they add unpredictable delays that affect the schedulability of multicore hard real-time systems. In recent years much effort has been put into modelling interference and proposing scheduling techniques to mitigate its negative effect. Using one of these models, we propose a scheduling technique, based on Integer Linear Programming (ILP) that, in combination with a task to core allocator, not only achieves a feasible schedule but also reduces the interference produced by shared hardware resources in the context of hard real-time multicore systems. The evaluation shows how both the interference is reduced (≈ 83.47%) and the schedulability is increased (≈ 12.25%) compared to traditional heuristics.

Role of 5G Networks in Healthcare Management System.

The present-day healthcare system operates on a 4G network, where the data rate needed for many IoT devices is impossible. Also, the latency involved in the network does not support the use of many devices in the network. The 5G-based cellular technology promises an effective healthcare management system with high speed and low latency. The 5G communication technology will replace the 4G technology to satisfy the increasing demand for high data rates. It incorporates higher frequency bands of around 100 MHz using millimetre waves and broadband modulation schemes. It is aimed at providing low latency while supporting real-time machine-to-machine communication. It requires a more significant number of antennas, with an average base station density three times higher than 4G. However, the rise in circuit and processing power for multiple antennas and transceivers deteriorates energy efficiency. Also, the data transmission power for 5G is three times higher than for 4G technology. One of the advanced processors used in today's mobile equipment is NVIDIA Tegra, which has a multicore system on chip (SoC) architecture with two ARM Cortex CPU cores to handle audio, images, and video. The state-of-the-art software coding using JAVA or Python has achieved smooth data transmission from mobile equipment, desktop or laptop through the internet with the support of 5G communication technology. This paper discusses some key areas related to 5G-based healthcare systems such as the architecture, antenna designs, power consumption, file protocols, security, and health implications of 5G networks.

Source-to-source translation for code-optimization

Multi-core design intends to serve a large market with user-oriented and highproductivity management as opposed to any other parallel system. Small numbers of processors, a frequent feature of current multi-core systems, are ideal for future generation of CPUs, where automated parallelization succeeds on shared space architectures. The multi-core compiler optimization platform CETUS (high-level to high-level compiler) offers initiates automatic parallelization in compiled programmes. This compiler’s infrastructure is built with C programmes in mind and is user-friendly and simple to use. It offers the significant parallelization passes and also the underlying empowering techniques, allows source-to-source conversions, and delivers these features. This compiler has undergone numerous benchmark investigations (techniques) and approach implementation iterations. It might enhance the programs’ parallel performance. The main drawback of advanced optimising compilers, however, is that they don’t provide runtime details like the program’s input data. The approaches presented in this paper facilitatedynamic optimization using CETUS. The large amount of proposed compiler analyses and modifications for parallelization is the last point. To research the behaviour as well as the throughput gains, we investigated both non-CETUS based and CETUS based parallelized program features in this work.

Energy-Efficient Cache Partitioning Using Machine Learning for Embedded Systems

Nowadays, embedded device applications have become partially correlated and can share platform resources. Cross-execution and sharing resources can cause memory access conflicts, especially in the Last Level Cache (LLC). LLC is a promising candidate for improving system performance on multicore embedded systems. It leads to a reduction in the number of high-latency main memory accesses. Currently, commercial devices can use cache partitioning. The software could better utilize the LLC and conserve energy by caching. This paper proposes a new energy-optimization model for embedded multicore systems based on a reconfigurable artificial neural network LLC architecture. The proposed model uses a machine-learning approach to express the reconfiguration of LLC, and can predict each task’s next interval LLC partitioning factor at runtime. The obtained experimental results reveal that the proposed model - compared to other algorithms - improves energy consumption by 28%, and gives 33% reduction in the LLC miss rate.

Passive Primary/Backup-Based Scheduling for Simultaneous Power and Reliability Management on Heterogeneous Embedded Systems

In addition to meeting the real-time constraint, power/energy efficiency and high reliability are two vital objectives for real-time embedded systems. Recently, heterogeneous multicore systems have been considered an appropriate solution for achieving joint power/energy efficiency and high reliability. However, power/energy and reliability are two conflict requirements due to the inherent redundancy of fault-tolerance techniques. Also, because of the heterogeneity of the system, the execution of the tasks, especially real-time tasks, in the heterogeneous system is more complicated than the homogeneous system. The proposed method in this paper employs a passive primary/backup technique to preserve the reliability requirement of the system at a satisfactory level and reduces power/energy consumption in heterogeneous multicore systems by considering real-time and peak power constraints. The proposed method attempts to map the primary and backup tasks in a mixed manner to benefit from the execution of the tasks in different core types and schedules the backup tasks after finishing the primary tasks to remove the overlap between the execution of the primary and backup tasks. Compared to the existing state-of-the-art methods, experimental results demonstrate our proposed method's power efficiency and effectiveness in terms of schedulability.

Symbiotic Organisms Search Optimization to Predict Optimal Thread Count for Multi-threaded Applications

Multicore systems have emerged as a cost-effective option for the growing demands for high-performance, low-energy computing. Thread management has long been a source of concern for developers, as overheads associated with it reduce the overall throughput of the multicore processor systems. One of the most complex problems with multicore processors is determining the optimal number of threads for the execution of multithreaded programs. To address this issue, this paper proposes a novel solution based on a modified symbiotic organism search (MSOS) algorithm which is a bio-inspired algorithm used for optimization in various engineering domains. This technique uses mutualism, commensalism and parasitism behaviours seen in organisms for searching the optimal solutions in the available search space. The algorithm is simulated on the NVIDIA DGX Intel-Xeon E5-2698-v4 server with PARSEC 3.0 benchmark suit. The results show that keeping the thread count equal to the number of processors available in the system is not necessarily the best strategy to get maximum speedup when running multithreaded programs. It was also observed that when programs are run with the optimal thread count, the execution time is substantially decreased, resulting in energy savings due to the use of fewer processors than are available in the system.

Learning-based Phase-aware Multi-core CPU Workload Forecasting

Predicting workload behavior during workload execution is essential for dynamic resource optimization in multi-processor systems. Recent studies have proposed advanced machine learning techniques for dynamic workload prediction. Workload prediction can be cast as a time series forecasting problem. However, traditional forecasting models struggle to predict abrupt workload changes. These changes occur because workloads are known to go through phases. Prior work has investigated machine-learning-based approaches for phase detection and prediction, but such approaches have not been studied in the context of dynamic workload forecasting. In this article, we propose phase-aware CPU workload forecasting as a novel approach that applies long-term phase prediction to improve the accuracy of short-term workload forecasting. Phase-aware forecasting requires machine learning models for phase classification, phase prediction, and phase-based forecasting that have not been explored in this combination before. Furthermore, existing prediction approaches have only been studied in single-core settings. This work explores phase-aware workload forecasting with multi-threaded workloads running on multi-core systems. We propose different multi-core settings differentiated by the number of cores they access and whether they produce specialized or global outputs per core. We study various advanced machine learning models for phase classification, phase prediction, and phase-based forecasting in isolation and different combinations for each setting. We apply our approach to forecasting of multi-threaded Parsec and SPEC workloads running on an eight-core Intel Core-i9 platform. Our results show that combining GMM clustering with LSTMs for phase prediction and phase-based forecasting yields the best phase-aware forecasting results. An approach that uses specialized models per core achieves an average error of 23% with up to 22% improvement in prediction accuracy compared to a phase-unaware setup.

A Nearest-Neighbor-Based Thermal Sensor Allocation and Temperature Reconstruction Method for 3-D NoC-Based Multicore Systems

To avoid overheating of 3-D network-on-chip (NoC)-based multicore systems, many researchers have used dynamic thermal management (DTM) techniques, which need embedded thermal sensors to provide accurate temperature information. However, only a few sensors can be embedded due to the limited hardware cost. So, it is crucial to find an appropriate way to allocate number-limited sensors at design time and reconstruct full-chip temperature accurately using the limited temperature information. However, the relationship between the non-sensor-allocated nodes and the sensor-allocated nodes modeled by the existing methods has a deviation from the actuality, which leads to an inaccurate temperature reconstruction. Another problem is that the existing methods depend highly on the training data. The estimation error can be significant when the running application’s traffic characteristic differs from the one in the offline phase. This article presents a sensor allocation method based on the cores’ spatial correlation, which is not dependent on the training data. Our allocation method contains two stages: 1) using our nearest-neighbor-based initialization algorithm to allocate sensors preliminarily and 2) using genetic algorithm (GA) to optimize the initial allocation. Besides, we use artificial neural network (ANN) to reconstruct the full-chip temperature. Compared with the state-of-the-art methods, our method can improve the average accuracy of the estimated temperature under different scenarios by 17.60%–88.63%. What is more, our approach has high flexibility and can adapt to different application scenarios with high accuracy with only one offline training.

Tuning block-parallel all-pairs shortest path algorithm for efficient multi-core implementa- tion.

Finding shortest paths in a weighted graph is one of the key problems in computer-science, which has numerous practical applications in multiple domains. This paper analyzes the parallel blocked all-pairs shortest path algorithm at the aim of evaluating the influence of the multi-core system and its hierarchical cache memory on the parameters of algorithm implementation depending on the size of the graph and the size of distance matrix’s block. It proposes a technique of tuning the block-size to the given multi-core system. The technique involves profiling tools in the tuning process and allows the increase of the parallel algorithm throughput. Computational experiments carried out on a rack server equipped with two Intel Xeon E5-2620 v4 processors of 8 cores and 16 hardware threads each have convincingly shown for various graph sizes that the behavior and parameters of the hierarchical cache memory operation don’t depend on the graph size and are determined only by the distance matrix’s block size. To tune the algorithm to the target multi-core system, the preferable block size can be found once for the graph size whose in-memory matrix representation is larger than the size of cache shared among all processor’s cores. Then this blocksize can be reused on graphs of bigger size for efficient solving the all-pairs shortest path problem

DAG Scheduling and Analysis on Multi-Core Systems by Modelling Parallelism and Dependency

With ever more complex functionalities being implemented in emerging real-time applications, multi-core systems are demanded for high performance, with directed acyclic graphs (DAG) being used to model functional dependencies. For a single DAG task, our previous work presented a concurrent provider and consumer (CPC) model that captures the node-level dependency and parallelism, which are the two key factors of a DAG. Based on the CPC, scheduling and analysis methods were constructed to reduce makespan and tighten the analytical bound of the task. However, the CPC-based methods cannot support multi-DAGs as the interference between DAGs (i.e., inter-task interference) is not taken into account. To address this limitation, this article proposes a novel multi-DAG scheduling approach which specifies the number of cores a DAG can utilise so that it does not incur the inter-task interference. This is achieved by modelling and understanding the workload distribution of the DAG and the system. By avoiding the inter-task interference, the constructed schedule provides full compatibility for the CPC-based methods to be applied on each DAG and reduces the pessimism of the existing analysis. Experimental results show that the proposed multi-DAG method achieves an improvement up to 80% in schedulability against the original work that it extends, and outperforms the existing multi-DAG methods by up to 60% for tightening the interference.

Computer applications: A novel architecture to improve the performance of audio visual applications

To attain the best audio-visual experience, the underlying computing platform should provide high performance in real time. The forthcoming computer systems consist of multicore processors to achieve a high performance-to-power ratio. The algorithms in visual computing are becoming highly complex to meet the requirements. According to the new design paradigm, a simultaneous exploration of multicore architecture and complicated algorithms is beneficial to achieve the design goals for visual systems. However, caches in multicore architecture multiply the timing unpredictability and that creates a serious challenge in running real-time audio/visual applications in multicore systems. In this work, we introduce a novel multicore architecture with miss tables inside level-1 caches to improve performance and decrease power consumption. Miss table holds block address information regarding the application being processed that causes cache misses. Miss table information is used for efficient selection of the blocks to be locked or victim blocks to be replaced. This approach improves predictability by locking important blocks inside the cache during the execution time. At the same time, this approach decreases average delay per task and total power consumption by reducing cache misses when the right cache blocks are locked and/or replaced. We simulate an 8-core architecture that has 2 levels of caches using the Moving Picture Experts Group (MPEG)-4 decoding and Fast Fourier Transform (FFT) workloads. Simulation results show that a reduction of 42% in mean delay per task and a reduction of 40% in total power consumption are achieved by locking 20% of the total level-1 instruction (I1) cache size.

ACCURATE: Accuracy Maximization for Real-Time Multicore Systems With Energy-Efficient Way-Sharing Caches

Improving result accuracy in approximate computing (AC)-based real-time applications without violating deadlines has recently become an active research domain. Execution time of AC real-time tasks can individually be separated into: execution of the mandatory part to obtain a result of acceptable quality, followed by a partial/complete execution of the optional part to improve the result accuracy of the initial result within a given deadline. However, obtaining higher result accuracy at the cost of enhanced execution time may lead to deadline violation, along with higher energy usage. We present ACCURATE, a novel hybrid offline–online approximate real-time scheduling approach that first schedules AC-based tasks on multicore with an objective to maximize result accuracy and determines operational processing speeds for each task constrained by system-wide power limit, deadline, and task dependency. At runtime, by employing a way-sharing technique (WH_LLC) at the last level cache (LLC), ACCURATE improves performance, which is further leveraged, to enhance result accuracy by executing more from the optional part and to improve the energy efficiency of the cache by turning off a controlled number of cache ways. ACCURATE also exploits the slacks either to improve the result accuracy of the tasks or to enhance the energy efficiency of the underlying system, or both. ACCURATE achieves 85% QoS with 36% average reduction in cache leakage consumption with a 24% average gain in energy-delay product (EDP) for a 4-core-based chip multiprocessor (CMP) with 6.4% average improvement in performance.

Efficient tasks scheduling in multicore systems integrated with hardware accelerators

Efficient tasks scheduling in multicore systems integrated with hardware accelerators

Thermal Sensor Placement for Multicore Systems Based on Low-Complex Compressive Sensing Theory

As the complexity of the multicore system grows, the large workload diversity results in serious thermal problems. In a practical way, the number of placed thermal sensors is usually limited due to the manufacturing cost. In recent years, the compressive sensing (CS) theory is proven as an efficient way to reconstruct the original signal by using fewer sampling data. However, due to the high computational complexity during the signal reconstruction, the CS theory is not appropriate to apply to the real-time temperature monitoring in the current multicore system. In this article, we propose a grid-based sensor placement approach to placement the number-limited thermal sensors on the target multicore system. On the other hand, we adopt the matrix inversion bypass (MIB) property to reduce the computational complexity of two widely used signal reconstruction approaches in CS theory [i.e., the orthogonal matching pursuit (OMP) and stagewise OMP (StOMP)]. Due to the characteristic of random sampling in CS theory, the complexity of thermal sensor placement for multicore systems can be reduced significantly. In addition, the proposed MIB-based temperature reconstruction method helps to satisfy the requirement of real-time temperature estimation. The experimental results show that the proposed approach can reduce 57%–93% average full-system temperature reconstruction error compared with the previous non-CS-based approaches. Besides, we can also reduce 22%–41% computing latency compared with the current CS-based reconstruction algorithm. Due to the MIB-based operation, we can bypass the matrix inversion operation for temperature reconstruction. Therefore, the hardware overhead of the temperature reconstruction unit can be reduced significantly. Compared with the conventional approaches, we can reduce 24%–87% area overhead and improve 50%–220% hardware efficiency.

A security-aware hardware scheduler for modern multi-core systems with hard real-time constraints

In this paper, we propose an online security-aware hardware scheduler, the so-called Secure And Fast hardware Scheduler (SAFAS), for real-time task scheduling in multi-core systems in the presence of schedule-based side-channel attacks. To avoid such attacks and ensure that all tasks meet their deadlines, SAFAS schedules critical tasks and their replicas using a hardware-based strict Least Slack Time first (LST) algorithm independently while it independently schedules the non-critical tasks using a hardware-based EDF algorithm. SAFAS enhances the system performance and reduces the chance of side-channel attacks due to the different processing cores allocated to each task in each scheduling interval. The hardware scheduler operates independently and in parallel with the multi-core system and hides the scheduling characteristics from adversaries. The software-based Earliest Deadline First (EDF) algorithm is also used for schedulability tests and feasibility analysis of hard real-time periodic tasks to maximize the number of tasks scheduled successfully in the multi-core system. SAFAS has been synthesized and simulated on a Xilinx Vivado 2018.2 and implemented on a Spartan-7 FPGA chip. Our experimental results indicate that SAFAS increases the performance of the system by 4.8 times as compared to previous state-of-the-art hardware schedulers while guaranteeing that all critical tasks and their replicas meet their deadlines.

RT-SEAT: A hybrid approach based real-time scheduler for energy and temperature efficient heterogeneous multicore platforms

The demand for heterogeneous multicore platforms is growing at a rapid pace in modern gadgets. Such platforms help cater to various types of applications and thus provide high resource utilization. As each task has a different execution time on different types of cores, it is very challenging to schedule tasks on such platforms. With the advancement in technology, it has become imperative to manage energy consumption and temperatures of cores in multicore platforms. Hence, in this work, we propose RT-SEAT, a hybrid real-time scheduler for energy and temperature-efficient heterogeneous multicore systems. Through extensive experimental analysis, we have found that RT-SEAT is able to schedule more tasks (up to 46.75%), save more energy (up to 6.89%), and reduce the average temperature of the cores by 20.45%, when the system workload varies from 50% to 100%, with respect to the state-of-the-art.

Specification of schedulability assumptions to leverage multiprocessor Analysis

In order to ease the early verification of uniprocessor real-time systems, the tool Cheddar provides a service that guarantees the applicability of a schedulability analysis method for a given architecture model. This verification service uses a catalog of design patterns.In this article, we propose to extend these patterns to multiprocessor architectures. Designing such extension is a challenge because the knowledge of both the software and the hardware architectures are essential to decide on the schedulability of a task set in that context. Indeed, parallel execution of tasks involves hardware resource sharing, that has in turn an effect on the task execution times. Currently, no general method is able to assess the schedulability of a high-performance multicore system with a limited level of pessimism, except if assumptions or usage restrictions are set to simplify the system analysis.So, the research community is developing multiple schedulability tests based on various assumptions which constrain the task models and their execution platforms. In this article, we propose a framework based on Prolog that allows engineers to verify the conditions to apply a test are met. Prolog facts model the software and hardware architecture, and the inference engine checks whether these facts conform to a design pattern associated to a given verification method.The design pattern compliance framework is integrated with the Cheddar tool. Three examples of multiprocessor analyses illustrate the proposal. A scalability analysis shows the tool is able to verify the compliance of architectures composed of 600 tasks and 60 cores, in less than 140s on a desktop computer.

MASTER: Reclamation of Hybrid Scratchpad Memory to Maximize Energy Saving in Multi-Core Edge Systems

Most modern multi-core edge devices work in outdoor situations with limited power supplies like energy harvester and batteries. Therefore, energy consumption is a fundamental issue in which the memory subsystem has a significant role. Scratchpad memories (SPM) can provide a broad potential for energy saving. Still, due to the insufficient SPM capacity in such edge devices, a rigorous SPM data allocation scheme is necessary to reduce the energy consumption of the memory subsystem. Emerging non-volatile memories (NVMs) are very useful to reduce the energy consumption of the memory subsystem. Compared with SRAM, NVMs have lower leakage power and higher density, but the read and write latencies of the NVMs are higher than the SRAM. Therefore, embedded and edge devices can take advantage of hybrid SPM composed of both NVM and SRAM to achieve further energy saving. This paper proposes MASTER, a task mapping, task scheduling, and dynamic SPM allocation scheme that efficiently utilizes the hybrid SPM space. To this end, we model the hybrid SPM allocation on a multi-core system with integer linear programming formulation to minimize the energy consumption of the memory subsystem. Experimental results show that MASTER improves the energy saving of the memory subsystem by up to 34 percent compared to EADA, which is a heuristic dynamic data allocation algorithm for multi-core systems with hybrid SPM.

Fast and Accurate Statistical Simulation of Shared-Memory Applications on Multicore Systems

Detailed cycle-accurate simulation of multicore systems is naturally slow. Statistical simulation is one alternative that permits trading off simulation speed for accuracy. However, there is a lack of effective memory locality models for multicore applications. Hence, existing statistical simulators neglect data-sharing between threads. Additionally, the standard method to speed up statistical simulations is to blindly reduce the trace length to be synthesized. While this gives good control over the speedup, it leaves the simulation error unbounded. In this work, we introduce a novel statistical simulation methodology for exploration of shared-memory multicore systems. It includes a new <underline xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><b>sha</b></u> ring- <underline xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><b>lo</b></u> cality <underline xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><b>m</b></u> odel ( <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Shalom</i> ) that captures and reproduces data-sharing in multithread applications. Furthermore, we propose a method to bound the simulation error for a particular metric while maximizing speedup. The technique works by monitoring the convergence of the statistical synthesis. It is referred to as <underline xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><b>con</b></u> vergence- <underline xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><b>de</b></u> termi <underline xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><b>n</b></u> istic <underline xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><b>s</b></u> imulation ( <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Condens</i> ). The combination of <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Shalom</i> and <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Condens</i> is around 130x faster than cycle-accurate simulations with reasonable accuracy loss. Our approach is also 5x faster than state-of-the-art sampling simulation under the same accuracy level. Compared to previous statistical simulators ignoring sharing, our approach is 2x more accurate for performance metrics and 8x more accurate for cache miss estimations.

An integration of autonomic computing with multicore systems for performance optimization in Industrial Internet of Things

AbstractThe goal of this work is to investigate how the self‐awareness characteristic of autonomic computing, paired with existing performance optimization rules, may be used in applications to minimise multi‐core processor performance concerns. The suggested self‐awareness technique can assist applications in self‐execution while also assisting other applications in executing in the system with optimal resource usage and reducing conflicts in a collaborative manner. It means self‐awareness is created in the application to get resources, schedules itself, running autonomically with respect to runtime variations in the applications and system parameters. Further, self‐aware applications would help collaboratively resolving the performance issues like; contention, bandwidth bottleneck, efficient task to core mapping, and performance monitoring through analysis in a dynamic collaborative multi‐core environment. To show the usefulness of this research, “Autonomic Computing Interface” (ACI) for is proposed Multicore systems. The proposed firmware as an interface between applications and the multi‐core system can dynamically handle performance issues with coordination of applications in an autonomic way. Also, in a highly dynamic execution environment the proposed runtime parameter tuning, existing performance improvement policies and self‐awareness approach in totality, for monitoring, analysis, and possibility for performance improvement would be effective as compared to the existing approaches which work in isolation.