Multi-core System Architecture Research Articles

A high performance real-time Interferometry Sensor System Architecture

Optical feedback or self-mixing interferometry technique has been widely used for sensing vibration, displacement, velocity, distance and flow applications. Such applications require an accurate and consistent output for real-time target measurements. Furthermore, array based sensing, as opposed to point sensing, is being increasingly pursued which requires multiple-input, parallel computing platform. In this article, we have proposed and developed a real-time interferometric sensor applications based multi-core system architecture and programming toolkit. To show that our system is useful in a variety of situations, we applied three algorithms of varying complexity and accuracy for displacement and vibration measurement. In order to prove the efficiency of proposed sensor processing system, we compared it performance and power consumption with a state of the art NXP LPCX54102 sensor processing and motion system architecture. When compared with the baseline multi-core system, the results show that our system improves the system performance upto 7.55 times, draws 15.6% less dynamic power and consumes 8.9 times less energy.

Multicore system architecture aspects and deployment

Abstract The crucial foundation in developing embedded safety-critical real-time systems based on multicore based platforms is the capability to combined different methodologies and approaches with a sound formal description of the system architecture. With such a system of methodologies and system architectures it is possible to develop a system satisfying all requirements and even being able to optimize the overall system towards domain specific goals. This article discusses activities in ARAMiS, which have been performed on system architecture level, including improvements of modeling existing architectures and design techniques concerning reliability, independence, segregation and determinism for deployment strategies.

Report on the first workshop on negative and null results in eScience

Report on the first workshop on negative and null results in eScience

High Level Model of Time Predictable Multitask Control Unit

The paper describes the high level abstract SystemC model of the multitask real time system. The authors put their main effort to obtain the highly time predictable system, The time predictability of real time embedded, electronic systems is identified and a concise survey of various approaches to the problem are given. The architecture of a single pipeline processor core with thread interleaving mechanism is emphasized. The scheduling algorithms that enable optimal utilization of the processing units are illustrated on examples. The main memory access control unit and the original memory system organization are described. Many simulation experiments conducted with single and multi-core system architecture implementation, allow obtaining results that prove advantages of the presented model.

DESIGNING AN ARCHITECTURE LEVEL MODEL FOR MULTI-CORE SYSTEMS

The Architecture Level Model (ALM) as a design in space exploration in the early phases of the design process can have a dramatic impact on the area, speed, and power consumption of the resulting systems. A multi-core system is an integrated circuit containing multiple processor cores that implements most of the functionality of a complex electronic system and some other components like FPGA/ASIC on a single chip. In this paper, we present a new approach to synthesize multi-core system architectures from Task Precedence Graphs (TPG) models. The front end engine applies efficient algorithm for scheduling and communication contention resolving to obtain the optimal multi- core system architecture in terms of number of processor cores, number of busses, task-to-processor/channel-to-bus mapping, optimal schedule, and Hardware/Software partition. The back end engine generates a System C simulation model using a well-known commercial tool model generation library to form the architecture level model. The viability and potential of the approach is demonstrated by a case study.

Realization of SMS4 Algorithm Based on Share Memory of the Heterogeneous Multi-Core Password Chip System

In order to meet the rapid demand of the modern cryptographic communication, heterogeneous multi-core password system architecture is set up based on shared memory in Xilinx XUP Virtex-II Pro chip in this paper. Under this architecture, the encryption and decryption of the SMS4 algorithm is realized fastly. Make a contrast with the homogeneous multi-core password system and the heterogeneous one-core password system’s performance in the execution time, throughput and resource utilization of the SMS4 algorithm.The experimental results show that the heterogeneous multi-core password system which based on shared memory has better performance.

PERFORMANCE EVALUATION OF MESSAGE PASSING VS. MULTITHREADING PARALLEL PROGRAMMING PARADIGMS ON MULTI-CORE SYSTEMS

Present and future multi-core computational system architecture attracts researchers to utilize this architecture as an adequate and inexpensive solution to achieve high performance computation for many problems. The multi-core architecture enables us to implement shared memory and/or message passing parallel processing paradigms. Therefore, we need appropriate standard libraries in order to utilize the resources of this architecture efficiently and effectively. In this work, we evaluate the performance of message passing using two versions of the well-known message passing interface (MPI) library: MPICH1 vs. MPICH2. Furthermore, we compared the performance of shared memory using OpenMP that supports multithreading with MPI. The results show that the performance when MPICH2 is used is better than MPICH1. The results indicate that multithreading performs better than message passing.