Multi-core Real-time System Research Articles

Interference-Aware Schedulability Analysis and Task Allocation for Multicore Hard Real-Time Systems

There has been a trend towards using multicore platforms for real-time embedded systems due to their high computing performance. In the scheduling of a multicore hard real-time system, there are interference delays due to contention of shared hardware resources. The main sources of interference are memory, cache memory, and the shared memory bus. These interferences are a great source of unpredictability and they are not always taken into account. Recent papers have proposed task models and schedulability algorithms to account for this interference delay. The aim of this paper is to provide a schedulability analysis for a task model that incorporates interference delay, for both fixed and dynamic priorities. We assume an implicit deadline task model. We rely on a task model where this interference is integrated in a general way, without depending on a specific type of hardware resource. There are similar approaches, but they consider fixed priorities. An allocation algorithm to minimise this interference (Imin) is also proposed and compared with existing allocators. The results show how Imin has the best rates in terms of percentages of schedulability and increased utilisation. In addition, Imin presents good results in terms of solution times.

NUMA-aware memory coloring for multicore real-time systems

Non-uniform memory access (NUMA) systems are characterized by varying memory latencies so that execution times may become unpredictable in a multicore real-time system. This results in overly conservative scheduling with low utilization due to loose bounds on a task’s worst-case execution time (WCET). This work contributes a controller/node-aware memory coloring (CAMC) allocator inside the Linux kernel for the entire address space to reduce access conflicts and latencies by isolating tasks from one another. CAMC improves timing predictability and performance over Linux’ buddy allocator and prior coloring methods. It provides core isolation with respect to banks and memory controllers for real-time systems. This work is the first to consider multiple memory controllers in real-time systems, combine them with bank coloring, and assess its performance on a NUMA architecture, to the best of our knowledge.

Energy-Efficient Task Scheduling in Design of Multithread Time Predictable Real-Time Systems

The paper presents balanced heuristic techniques of static tasks scheduling in multi-core real-time system architecture. The main objective was to minimize the energy consumed by the system without causing deadlines to be missed. The authors proposed a few scheduling scenarios based on modifications of different parameters of the system and defined appropriate algorithms. The methodology was verified and tested on the original hardware platform of the system developed by the authors. The system consists of the reconfigurable set of cores based on an interleaved pipeline processing scheme. The entire system was modeled as original IP at the RTL level in VERILOG and implemented on a Virtex7 FPGA platform. The tasks were executed as a set of programs based on Malardalen WCET benchmarks; commonly used by the PRET community for validation time predictable systems and worst-case analyses. Many series of experiments were carried out and the results validated the approach and showed that it is possible to radically reduce the energy consumed by the system while retaining timing conditions (i.e., deadlines). The authors gathered and discussed results and formulated a set of recommendations for the safety real-time system’s design flowchart aimed to minimize the energy consumed by the system.

Experiences of Civil Certification of Multi-Core Processing Systems in Commercial and Military Avionics, Integration Activities, and Analysis

<div class="section abstract"><div class="htmlview paragraph">Avionics systems are currently undergoing a transition from single core processor architectures to multi-core processor architectures. This transition enables significant advantages in reduction in size, weight, power (SWaP) and cost. However, avionics hardware and software certification policies and guidance are evolving as research and experience is gained with multi-core processor architectures. The unique challenges of using multi-core processors in certified avionics will be discussed. The requirements for a virtualization platform supporting multiple real-time operating system (RTOS) partitions on a multi-core processor used in safety-critical avionics systems are defined, including the ability to support multiple design assurance levels (DAL) on multiple cores, fault isolation and containment, static configuration as per ARINC 653, role-based development as per DO-297, and robust partitioning to reduce cost of incremental certification. The paper will present a collaborative approach undertaken by a leading avionics system supplier and a leading safety-critical commercial-off-the-shelf (COTS) RTOS supplier in the development of a multi-core real-time system with DO-178C DAL A software and DO-254 DAL A hardware safety certification on an FAA Program of Record (PoR). The approach taken to comply with FAA CAST-32A objectives will be presented. Particular focus is provided for integration activities and program specific analysis performed by the IMA application developer and integrator to guarantee determinism in the deployed system. Using the approach defined under the PoR, the application developer performs activities including foot-printing under worst-case execution time (WCET) loads and application of numerical methods to predict interference effects. The IMA integrator uses this data to define a performance restricted environment (PRE) and uses WCET verification in the PRE. Tools, analysis methods, and sample results will be presented. The method to capture results is discussed. Finally the paper includes lessons learned during the program.</div></div>

Efficient Worst-Case Temperature Evaluation for Thermal-Aware Assignment of Real-Time Applications on MPSoCs

The reliability of multiprocessor system-on-chips (MPSoCs) is nowadays threatened by high chip temperatures leading to long-term reliability concerns and short-term functional errors. High chip temperatures might not only cause potential deadline violations, but also increase cooling costs and leakage power. Pro-active thermal-aware allocation and scheduling techniques that avoid thermal emergencies are promising techniques to reduce the peak temperature of an MPSoC. However, calculating the peak temperature of hundreds of design alternatives during design space exploration is time-consuming, in particular for unknown input patterns and data. In this paper, we address this challenge and present a fast analytic method to calculate a non-trivial upper bound on the maximum temperature of a multi-core real-time system with non-deterministic workload. The considered thermal model is able to address various thermal effects like heat exchange between neighboring cores and temperature-dependent leakage power. Afterwards, we integrate the proposed thermal analysis method into a design-space exploration framework to optimize the task to processing component assignment. Finally, we apply the proposed method in various case studies to explore thermal hot spots and to optimize the task to processing component assignment.

The ASDEX upgrade digital video processing system for real-time machine protection

This paper describes the design, implementation, and operation of the Video Real-Time (VRT) diagnostic system of the ASDEX Upgrade plasma experiment and its integration with the ASDEX Upgrade Discharge Control System (DCS). Hot spots produced by heating systems erroneously or accidentally hitting the vessel walls, or from objects in the vessel reaching into the plasma outer border, show up as bright areas in the videos during and after the reaction. A system to prevent damage to the machine by allowing for intervention in a running discharge of the experiment was proposed and implemented. The VRT was implemented on a multi-core real-time Linux system. Up to 16 analog video channels (color and b/w) are acquired and multiple regions of interest (ROI) are processed on each video frame. Detected critical states can be used to initiate appropriate reactions – e.g. gracefully terminate the discharge. The system has been in routine operation since 2007.

A Novel Cache Sharing Scheme and Implementation in Multi-Core Real-Time Linux System

Memory allocation and management of real-time task and sub real-time task have been becoming the hot problem that people concern all the time. Page coloring technology is a kind of practical method which can realize isolation of cache space. This article aimed at the problem of cache resource competition caused by shared memory on multi-core real-time system, to solve the collision of cache visit, put forward the scheme of cache space isolation based on page coloring technology and the realization method. The problem that data collide with the visit on cache can be finally avoided, by dividing the shared cache space.

System Design for Real-time Image Processing Based on Multi-core DSP

In the process of real time image processing, the amount of image processing computing and data is very large, the use of single core or a single DSP can not meet the needs of real-time image processing. This paper designs the new generation multi-core DSP real-time image processing system, the system is a multi-core high performance DSP as the core circuit, and also uses FPGA counterweight device, high-speed data interface and high-speed external memory, to improve the data cache speed and data bandwidth, and the system satisfies the design of low loss and high computational performance. In order to verify the validity and reliability of the system, this paper uses the Hyper Lynx software to carry on the simulation test for the system, and sets the IP and sub net mask of image real time processing to obtain the eye and timing diagram of real-time image processing. Finally, the system image processing performance results can be obtained by the joint debugging, the simulation test results can be seen that the speed of real-time image processing is quick, and the rate of correct recognition is high, which can satisfy the need of real-time image processing, to provide the technical reference for the design of real time image processing system