Abstract
The paper presents balanced heuristic techniques of static tasks scheduling in multi-core real-time system architecture. The main objective was to minimize the energy consumed by the system without causing deadlines to be missed. The authors proposed a few scheduling scenarios based on modifications of different parameters of the system and defined appropriate algorithms. The methodology was verified and tested on the original hardware platform of the system developed by the authors. The system consists of the reconfigurable set of cores based on an interleaved pipeline processing scheme. The entire system was modeled as original IP at the RTL level in VERILOG and implemented on a Virtex7 FPGA platform. The tasks were executed as a set of programs based on Malardalen WCET benchmarks; commonly used by the PRET community for validation time predictable systems and worst-case analyses. Many series of experiments were carried out and the results validated the approach and showed that it is possible to radically reduce the energy consumed by the system while retaining timing conditions (i.e., deadlines). The authors gathered and discussed results and formulated a set of recommendations for the safety real-time system’s design flowchart aimed to minimize the energy consumed by the system.
Highlights
One of the most important properties of contemporary real-time embedded systems is their predictability
Due to the fact that we focused on the safety, real-time system design process our approach concerns static scheduling problems
GOAL FUNCTION To formulate the goal function of our scheduler assume that: Th denotes the set of all threads executed by the system; PE is the set of all processing elements; E(pei) represents the energy consumed by the i-th processing element; M(pei) denotes the mapping of tasks to a given pei and pt(ti) is the processing time of the task ti
Summary
One of the most important properties (and the most crucial requirement) of contemporary real-time embedded systems is their predictability. Strong competition between vendors implies that they offer the equipment supporting new, sophisticated functionalities This intricacy of electronic embedded system’s architectures may discard their predictability and the engineers involved in the design process are required to spend hundreds of hours to keep the systems predictable. The paper presents the contribution in the research on time-predictable systems. The paper consists of seven parts: the second section analyzes the related work and other solutions concerning hardware as well as software elements of time-predictable real-time systems. The fourth section formulates the motivation of the work and main contributions of the paper. The section number eighth describes the testing environment and shows the results of the experiments and the final, ninth section summarizes the paper and presents some conclusions
Sign-in/Register to view highlights & summary Sign-in/Register to access full text options 
Free) 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a call
