Multi-core Machines Research Articles

An optimized bitonic sorting strategy with midpoint-based dynamic communication

This paper proposes an optimized Bitonic sorting (OBS) strategy with midpoint-based dynamic communication. Our OBS strategy uses the midpoint-weight list ranking to improve complexity and reduce time of sorting on parallel and distributed systems. Applying a better key in the PE-list ranking can find the right place of (Pi, Pj) and improve communication time significantly (i.e., fewer iterations, better synchronization in each iteration, faster convergence to the result), while most of coarse-grain parallel sorting (P<N) approaches improve only a large amount of data exchange (N/P) in each of static(s(s+1)/2) iterations. Theoretically, the OBS method can reduce fixed (s(s+1)/2) iterations to 1,2,3,…, or s=log2P iterations, which are improved over those (≤s(s+1)/2 iterations) of the dynamic DCES method. In performance evaluation, sorting was accomplished on multicore machines. Experimental results showed that our optimized OBS outperforms those of the dynamic DCES about 35%–40% and those of the static LBM about 51%–54% (for N=10 to 100 million elements on an 8-multicore computer).

Ultra fast, accurate PET image reconstruction for the Siemens hybrid MR/BrainPET scanner using raw LOR data.

Fast PET image reconstruction algorithms usually use a Line-of-Response (LOR) preprocessing step where the detected raw LOR data are interpolated either to evenly spaced sinogram projection bins or alternatively to a generic projection space as for example proposed by the PET Reconstruction Software Toolkit (PRESTO) [1]. In this way, speed-optimised, versatile geometrical projectors can be implemented for iterative image reconstruction independent of the underlying scanner geometry. However, all strategies of projection data interpolation unavoidably lead to a loss of original information and result in some degradation of image quality. Here, direct LOR reconstructions overcome this evident drawback at cost of a massively enhanced computational burden. Therefore, computational optimisation techniques are essential to make such demanding approaches attractive and economical for widespread usage in the clinical environment. In this paper, we demonstrate for the Siemens Hybrid MR/BrainPET with 240 million physical LORs that a very fast quantitative direct LOR reconstruction can be realized using a modified version of PRESTO. Now, PRESTO is also capable to directly use sets of symmetric physical LORs instead of interpolating LORs to a generic projection space. Exploiting basic scanner symmetries together with the technique of Single Instruction Multipe Data (SIMD) and Simultaneous Multi-Threading (SMT) results in an overall calculation time of 2-3 minutes per frame on a single multi-core machine, i.e. neither requiring a cluster of mutliple machines nor Graphics Processing Units (GPUs).

Modeling and analysis of performances for concurrent multithread applications on multicore and graphics processing unit systems

SummaryThe capabilities of multicore processors lead them to be widely adopted in systems at any scale, since their are able to provide more computing power at a lower consumption and dissipation cost. System designers are challenged to a deeper understanding of multicore functioning in order to fully exploit them while keeping the optimal balance between cores utilization and optimal throughput, response time and energy usage.Besides the advancement of general purpose CPUs, the same technological evolution leads to the rise of GPUs, dramatic evolution of graphical coprocessors, that are now affordable, efficient, dedicated computing units, capable of parallel computing and equipped with facilities that make them suited for supporting the main CPU of a system in running ordinary applications. The availability of commercial off‐the‐shelf (COTS) multicore computers, eventually equipped with one or more GPUs, makes them the basic building block of data centers devoted to cloud applications or scientific computing.The way to optimal exploitation of such a wide amount of computing power passes through the ability of matching the best scheduling of hardware resources with the software characteristics of the applications. This requires appropriate models and evaluation methods.Simulation and analytical techniques are essential tools to support the design and the management process of such architectures, but a sound characterization of the workloads is required. Typical workloads consist in multithreaded applications, with different characteristics, that dynamically span over the cores of multiple machines, connected by fast networks.In this paper we propose several parametric performance models for different configurations of multicore machines, with or without GPU support, running multiple class multithreaded applications, aiming to supply a detailed modeling help for complex data centers. Copyright © 2015 John Wiley &amp; Sons, Ltd.

Halvade: scalable sequence analysis with MapReduce.

Motivation: Post-sequencing DNA analysis typically consists of read mapping followed by variant calling. Especially for whole genome sequencing, this computational step is very time-consuming, even when using multithreading on a multi-core machine.Results: We present Halvade, a framework that enables sequencing pipelines to be executed in parallel on a multi-node and/or multi-core compute infrastructure in a highly efficient manner. As an example, a DNA sequencing analysis pipeline for variant calling has been implemented according to the GATK Best Practices recommendations, supporting both whole genome and whole exome sequencing. Using a 15-node computer cluster with 360 CPU cores in total, Halvade processes the NA12878 dataset (human, 100 bp paired-end reads, 50× coverage) in <3 h with very high parallel efficiency. Even on a single, multi-core machine, Halvade attains a significant speedup compared with running the individual tools with multithreading.Availability and implementation: Halvade is written in Java and uses the Hadoop MapReduce 2.0 API. It supports a wide range of distributions of Hadoop, including Cloudera and Amazon EMR. Its source is available at http://bioinformatics.intec.ugent.be/halvade under GPL license.Contact: jan.fostier@intec.ugent.beSupplementary information: Supplementary data are available at Bioinformatics online.

A parallel processing approach to dynamic simulations of combined transmission and distribution systems

Abstract Simulating a power system with both transmission and distribution networks modeled in detail is a huge computational challenge. In this paper, a Schur-complement-based domain decomposition algorithm is proposed to provide accurate, detailed dynamic simulations of such systems. The simulation procedure is accelerated with the use of parallel programming techniques, taking advantage of the parallelization opportunities inherent to domain decomposition algorithms. The proposed algorithm is general, portable and scalable on inexpensive, shared-memory, multi-core machines. A large-scale test system is used for its performance evaluation.

Hybrid Shared-aware Cache Coherence Transition Strategy

Chip-multiprocessors have played a significant role in real parallel computer architecture design. For integrating tens of cores into a chip, designs tend towards with physically distributed last level caches. This naturally results in a Non-Uniform Cache Access design, where on-chip access latencies depend on the physical distances between requesting cores and home cores where the data is cached. Therefore, data movement and management impact access latency and power consumption. Remote misses limit the performance of multi-threaded applications, so using data locality is fundamental importance in Chip-multiprocessors. In this work we observed that a shared data writing behavior dramatically wastes precious on-chip cache resource and seriously affects the whole system performance. Therefore, we emphasis on improving the performance of applications that exhibit high data sharing, and propose a new prediction mechanism to predict accurately the impact of shared data and a scalable, efficient hybrid shared-aware cache coherence transition strategy which collaborate with directory-based MESI cache coherence protocol. In order to evaluate our proposal transition strategy, we experiment with the NAS Parallel Benchmarks and a modern Intel Harpertown multi-core machine. Results show the whole performance gains of up to 21% opposed to the traditional write-invalidate cache coherence transition strategy.

Lock Cohorting

Multicore machines are quickly shifting to NUMA and CC-NUMA architectures, making scalable NUMA-aware locking algorithms, ones that take into account the machine's nonuniform memory and caching hierarchy, ever more important. This article presents lock cohorting , a general new technique for designing NUMA-aware locks that is as simple as it is powerful. Lock cohorting allows one to transform any spin-lock algorithm, with minimal nonintrusive changes,into a scalable NUMA-aware spin-lock. Our new cohorting technique allows us to easily create NUMA-aware versions of the TATAS-Backoff, CLH, MCS, and ticket locks, to name a few. Moreover, it allows us to derive a CLH-based cohort abortable lock, the first NUMA-aware queue lock to support abortability. We empirically compared the performance of cohort locks with prior NUMA-aware and classic NUMA-oblivious locks on a synthetic micro-benchmark, a real world key-value store application memcached, as well as the libc memory allocator. Our results demonstrate that cohort locks perform as well or better than known locks when the load is low and significantly out-perform them as the load increases.

Parallel visual data restoration on multi-GPGPUs using stencil-reduce pattern

In this paper, a highly effective parallel filter for visual data restoration is presented. The filter is designed following a skeletal approach, using a newly proposed stencil-reduce, and has been implemented by way of the FastFlow parallel programming library. As a result of its high-level design, it is possible to run the filter seamlessly on a multicore machine, on multi-GPGPUs, or on both. The design and implementation of the filter are discussed, and an experimental evaluation is presented.

Design and simulation of material-integrated distributed sensor processing with a code-based agent platform and mobile multi-agent systems.

Multi-agent systems (MAS) can be used for decentralized and self-organizing data processing in a distributed system, like a resource-constrained sensor network, enabling distributed information extraction, for example, based on pattern recognition and self-organization, by decomposing complex tasks in simpler cooperative agents. Reliable MAS-based data processing approaches can aid the material-integration of structural-monitoring applications, with agent processing platforms scaled to the microchip level. The agent behavior, based on a dynamic activity-transition graph (ATG) model, is implemented with program code storing the control and the data state of an agent, which is novel. The program code can be modified by the agent itself using code morphing techniques and is capable of migrating in the network between nodes. The program code is a self-contained unit (a container) and embeds the agent data, the initialization instructions and the ATG behavior implementation. The microchip agent processing platform used for the execution of the agent code is a standalone multi-core stack machine with a zero-operand instruction format, leading to a small-sized agent program code, low system complexity and high system performance. The agent processing is token-queue-based, similar to Petri-nets. The agent platform can be implemented in software, too, offering compatibility at the operational and code level, supporting agent processing in strong heterogeneous networks. In this work, the agent platform embedded in a large-scale distributed sensor network is simulated at the architectural level by using agent-based simulation techniques.

Model order reduction with oblique projections for large scale wave propagation

There are many applications in which it is necessary to solve large scale parametrized wave propagation problems repeatedly. This is still quite a challenging task, even with the largest available computer clusters. In this paper we will discuss the application of Model Order Reduction (MOR) to problems in seismic petroleum exploration, with the aim of diminishing the necessary computing time by a significant factor. We consider POD and some variants. POD is a Model Order Reduction technique that uses snapshots of a few simulations in order to quickly compute related problems with similar accuracy. The method of lines via a Petrov–Galerkin approximation that uses the snapshots as basis functions is the considered approach. The order reduction comes from projecting the wave equation discretized in space to the subspace spanned by the snapshots. This has been shown earlier to work well in two dimensions. The challenge in three dimensions comes from the size of the spatial meshes required and the fact that the method usually requires a number of snapshots that do not fit in fast memory, even for current high end multicore machines. Parallelization is not an option since it is already used for other aspects of this massive problem.

A Computational Framework for Implementation of Neural Networks on Multi-Core Machine

Abstract This paper presents a computational framework, the Generic Programmable Neural Network (GPNN), for efficient implementation of Back-Propagation based neural learning algorithms running on multi-core machines. GPNN has three components: parallelization of neural learning, abstraction of network components, and compile-time generalization. Together these computational components make GPNN an efficient framework for fast implementation of back-propagation based neural learning algorithms, and provide flexibility and reusability for modifying neural network topologies. The GPNN was applied to four different neural learning algorithms: classic back-propagation (BP), quick propagation (QP), resilient propagation (RP) and Levenberg-Marquardt (LM) algorithm. Experiments were conducted to evaluate the effectiveness of GPNN, and results show that the neural learning algorithms implemented in GPNN are more efficient than their respective functions provided by Matlab.

Improved Parallel Lexical Analysis Using OpenMP on Multi-core Machines

Abstract Lexical Analysis is the first and foremost step of a compiler. Various attempts have been made to improve the lexical analysis phase by exploiting the inherent parallel processing capability of multi-core machines. In this paper we present an approach for doing parallel lexical analysis using OpenMP. We demonstrate the improvement in lexical analysis phase by automatically generating C programs having up to 10,000 potentially parallel constructs like if..else, for, while loops, switch..case etc. The maximum speedup achieved for 7 CPUs is 6.84.

Parallel Text Mining in Multicore Systems Using FP-tree Algorithm

Frequent keyword mining (FKM) is a useful tool for discovering frequently occurring keywords in data. Many algorithms have been developed to speed up mining performance on single core systems. Unfortunately, when the dataset size is huge, both the memory use and computational cost can still be extremely expensive. In our paper, we try to parallelize the FP-Growth algorithm on multicore machines. We partition the huge database, into the number of cores, and utilize the combined strength of all the cores, to achieve maximum performance. We propose to use the generated FP Tree and its rules for the Trend analysis of news data.

Fast Parallel All-Subgraph Enumeration Using Multicore Machines

Enumerating all subgraphs of an input graph is an important task for analyzing complex networks. Valuable information can be extracted about the characteristics of the input graph using all-subgraph enumeration. Notwithstanding, the number of subgraphs grows exponentially with growth of the input graph or by increasing the size of the subgraphs to be enumerated. Hence, all-subgraph enumeration is very time consuming when the size of the subgraphs or the input graph is big. We propose a parallel solution namedSubenumwhich in contrast to available solutions can perform much faster. Subenum enumerates subgraphs using edges instead of vertices, and this approach leads to a parallel and load-balanced enumeration algorithm that can have efficient execution on current multicore and multiprocessor machines. Also, Subenum uses a fast heuristic which can effectively accelerate non-isomorphism subgraph enumeration. Subenum can efficiently use external memory, and unlike other subgraph enumeration methods, it is not associated with the main memory limits of the used machine. Hence, Subenum can handle large input graphs and subgraph sizes that other solutions cannot handle. Several experiments are done using real-world input graphs. Compared to the available solutions, Subenum can enumerate subgraphs several orders of magnitude faster and the experimental results show that the performance of Subenum scales almost linearly by using additional processor cores.

Fine-grained preemption analysis for latency investigation across virtual machines

This paper studies the preemption between programs running in different virtual machines on the same computer. One of the current monitoring methods consist of updating the average steal time through collaboration with the hypervisor. However, the average is insufficient to diagnose abnormal latencies in time-sensitive applications. Moreover, the added latency is not directly visible from the virtual machine point of view. The main challenge is to recover the cause of preemption of a task running in a virtual machine, whether it is a task on the host computer or in another virtual machine. We propose a new method to study thread preemption crossing virtual machines boundaries using kernel tracing. The host computer and each monitored virtual machine are traced simultaneously. We developed an efficient and portable trace synchronization method, which is required to account for time offset and drift that occur within each virtual machine. We then devised an algorithm to recover the root cause of preemption between threads at every level. The algorithm successfully detected interactions between multiple competing threads in distinct virtual machines on a multi-core machine.

Evaluation of Selected Resource Allocation and Scheduling Methods in Heterogeneous Many-Core Processors and Graphics Processing Units

Abstract Heterogeneous many-core computing resources are increasingly popular among users due to their improved performance over homogeneous systems. Many developers have realized that heterogeneous systems, e.g. a combination of a shared memory multi-core CPU machine with massively parallel Graphics Processing Units (GPUs), can provide significant performance opportunities to a wide range of applications. However, the best overall performance can only be achieved if application tasks are efficiently assigned to different types of processor units in time taking into account their specific resource requirements. Additionally, one should note that available heterogeneous resources have been designed as general purpose units, however, with many built-in features accelerating specific application operations. In other words, the same algorithm or application functionality can be implemented as a different task for CPU or GPU. Nevertheless, from the perspective of various evaluation criteria, e.g. the total execution time or energy consumption, we may observe completely different results. Therefore, as tasks can be scheduled and managed in many alternative ways on both many-core CPUs or GPUs and consequently have a huge impact on the overall computing resources performance, there are needs for new and improved resource management techniques. In this paper we discuss results achieved during experimental performance studies of selected task scheduling methods in heterogeneous computing systems. Additionally, we present a new architecture for resource allocation and task scheduling library which provides a generic application programming interface at the operating system level for improving scheduling polices taking into account a diversity of tasks and heterogeneous computing resources characteristics.

Deployment of query plans on multicores

Efficient resource scheduling of multithreaded software on multicore hardware is difficult given the many parameters involved and the hardware heterogeneity of existing systems. In this paper we explore the efficient deployment of query plans over a multicore machine. We focus on shared query systems, and implement the proposed ideas using SharedDB. The goal of the paper is to explore how to deliver maximum performance and predictability, while minimizing resource utilization when deploying query plans on multicore machines. We propose to use resource activity vectors to characterize the behavior of individual database operators. We then present a novel deployment algorithm which uses these vectors together with dataflow information from the query plan to optimally assign relational operators to physical cores. Experiments demonstrate that this approach significantly reduces resource requirements while preserving performance and is robust across different server architectures.

Issues in Implementation of Parallel Parsing on Multi-Core Machines

The advent of multi-core architecture has highly influenced the area of high performance computing. Parallel compilation is the area which still needs significant improvement by the use of this architecture. Recent research has shown some improvement in lexical analysis phase. But it is difficult to implement the same technique in parsing phase. This paper highlights some issues related to implementation of parallel parsing on multi-core machines.

Couillard: Parallel programming via coarse-grained Data-flow Compilation

Abstract Data-flow is a natural approach to parallelism. However, describing dependencies and control between fine-grained data-flow tasks can be complex and present unwanted overheads. TALM (TALM is an Architecture and Language for Multi-threading) introduces a user-defined coarse-grained parallel data-flow model, where programmers identify code blocks, called super-instructions, to be run in parallel and connect them in a data-flow graph. TALM has been implemented as a hybrid Von Neumann/data-flow execution system: the Trebuchet . We have observed that TALM’s usefulness largely depends on how programmers specify and connect super-instructions. Thus, we present Couillard , a full compiler that creates, based on an annotated C-program, a data-flow graph and C-code corresponding to each super-instruction. We show that our toolchain allows one to benefit from data-flow execution and explore sophisticated parallel programming techniques, with small effort. To evaluate our system we have executed a set of real applications on a large multi-core machine. Comparison with popular parallel programming methods shows competitive speedups, while providing an easier parallel programing approach. More specifically, for an application that follows the wavefront method, running with big inputs, Trebuchet achieved up to 4.7% speedup over Intel® TBB novel flow-graph approach and up to 44% over OpenMP.

Parallel family trees for transfer matrices in the Potts model

The computational cost of transfer matrix methods for the Potts model is related to the question in how many ways can two layers of a lattice be connected? Answering the question leads to the generation of a combinatorial set of lattice configurations. This set defines the configuration space of the problem, and the smaller it is, the faster the transfer matrix can be computed. The configuration space of generic (q,v) transfer matrix methods for strips is in the order of the Catalan numbers, which grows asymptotically as O(4m) where m is the width of the strip. Other transfer matrix methods with a smaller configuration space indeed exist but they make assumptions on the temperature, number of spin states, or restrict the structure of the lattice. In this paper we propose a parallel algorithm that uses a sub-Catalan configuration space of O(3m) to build the generic (q,v) transfer matrix in a compressed form. The improvement is achieved by grouping the original set of Catalan configurations into a forest of family trees, in such a way that the solution to the problem is now computed by solving the root node of each family. As a result, the algorithm becomes exponentially faster than the Catalan approach while still highly parallel. The resulting matrix is stored in a compressed form using O(3m×4m) of space, making numerical evaluation and decompression to be faster than evaluating the matrix in its O(4m×4m) uncompressed form. Experimental results for different sizes of strip lattices show that the parallel family trees (PFT) strategy indeed runs exponentially faster than the Catalan Parallel Method (CPM), especially when dealing with dense transfer matrices. In terms of parallel performance, we report strong-scaling speedups of up to 5.7× when running on an 8-core shared memory machine and 28× for a 32-core cluster. The best balance of speedup and efficiency for the multi-core machine was achieved when using p=4 processors, while for the cluster scenario it was in the range p∈[8,10]. Because of the parallel capabilities of the algorithm, a large-scale execution of the parallel family trees strategy in a supercomputer could contribute to the study of wider strip lattices.