Multi-core GPUs Research Articles

Block Inverse Preconditioner for Implicit Time Integration in Finite Element Micromagnetic Solvers

A block-inverse preconditioner (BIP) is proposed to accelerate solving implicit time integration in the context of Newton–Krylov approach used in micromagnetic simulations for solving the Landau–Lifshitz–Gilbert equation. A coefficient matrix is generated and stored for the linear system of Newton method. BIP is formulated by subdividing the coefficient matrix into small blocks and directly inverting them. The cost of preconditioning is low since inverting and multiplying small blocks is fast, which can be further minimized by parallel computing on multicore CPUs or GPUs. The effectiveness, speed, robustness, and scalability of BIP is demonstrated by numerical simulation experiments. Comparisons to incomplete LU preconditioning methods are conducted to demonstrate the effectiveness of BIP.

Cost‐efficient numerical algorithm for solving the linear inverse problem of finding a variable magnetization

The paper is devoted to developing an original cost‐efficient algorithm for solving the inverse problem of finding a variable magnetization in a rectangular parallelepiped. The problem is ill‐posed and is described by the integral Fredholm equation.It is shown that after discretization of the area and approximation of the integral operator, this problem is reduced to solving a system of linear algebraic equations with the Toeplitz‐block‐Toeplitz matrix. We have constructed the memory efficient variant of the stabilized biconjugate gradient method BiCGSTABmem. This optimized algorithm exploits the special structure of the matrix to reduce the memory requirements and computing time.The efficient implementation is developed for multicore CPU and GPU. A series of the model problems with synthetic and real magnetic data are solved. Investigation of efficiency and speedup of parallel algorithm is performed.

Data-cloning SMC2: A global optimizer for maximum likelihood estimation of latent variable models

A data-cloning SMC2 algorithm is proposed as a general-purpose, global optimization routine for the maximum likelihood estimation of models with latent variables. In the SMC2 phase, the method first marginalizes out the latent variable(s) by applying one layer of SMC at a fixed parameter value and then searches for the optimal parameters through another layer of SMC. The data-cloning phase is deployed to ensure global convergence by dampening multi-modality and to reduce the Monte Carlo error associated with SMC. This new method has broad applicability and is massively parallelizable through leveraging modern multi-core CPU or GPU computing.

Energy Efficient Chip-to-Chip Wireless Interconnection for Heterogeneous Architectures

Heterogeneous multichip architectures have gained significant interest in high-performance computing clusters to cater to a wide range of applications. In particular, heterogeneous systems with multiple multicore CPUs, GPUs, and memory have become common to meet application requirements. The shared resources like interconnection network in such systems pose significant challenges due to the diverse traffic requirements of CPUs and GPUs. Especially, the performance and energy consumption of inter-chip communication have remained a major bottleneck due to limitations imposed by off-chip wired links. To overcome these challenges, we propose a wireless interconnection network to provide energy-efficient, high-performance communication in heterogeneous multi-chip systems. Interference-free communication between GPUs and memory modules is achieved through directional wireless links, while omnidirectional wireless interfaces connect cores in the CPUs with other components in the system. Besides providing low-energy, high-bandwidth inter-chip communication, the wireless interconnection scales efficiently with system size to provide high performance across multiple chips. The proposed inter-chip wireless interconnection is evaluated on two system sizes with multiple CPU and multiple GPU chips, along with main memory modules. On a system with 4 CPU and 4 GPU chips, application runtime is sped up by 3.94×, packet energy is reduced by 94.4%, and packet latency is reduced by 58.34% as compared to baseline system with wired inter-chip interconnection.

NI P2P powered multi FPGA real-time data processing on tokamak diagnosis systems

On tokamaks, there are many diagnostics, which need real-time data acquisition and processing to provide useful information for plasma control. Some of the diagnostics required fast processing of multiple very high sampling rate signals. It is often difficult to achieve even with modern multi-core CPUs or GPUs. Moving large amount of data from the digitizers to the system ram will hurt the deterministic performance significantly. FPGA data pre-processing is a better choice when the data large and deterministic performance is required. When the task is too heavy for a single FPGA to implement, transfer large data between FPGAs is also required. On the polarimeter-interferometer diagnostics on J-TEXT, in order to calculate the density profile of the plasma in real-time, multiple chords of line-integrated density must be calculated first. The data acquisition system for the polarimeter-interferometer is equipped with 5 FlexRIO FPGAs, only one is acquiring the reference signal. Density calculation for every probing chord needs the reference signal. So this signal needs to be transferred to other FPGAs with strict real-time requirement. Mismatching a single sample, the result would be completely incorrect. NI P2P streaming allow the FPGA to transfer data without burdening the process. In the paper, the determinism characteristic and other performance of the P2P streaming is tested, and a mechanism to align local digitized samples with P2P streamed samples is presented. These results can be applied to other real-time data processing system that requires multiple FPGAs.

A Dual Heterogeneous Island Genetic Algorithm for Solving Large Size Flexible Flow Shop Scheduling Problems on Hybrid Multicore CPU and GPU Platforms

The flexible flow shop scheduling problem is an NP-hard problem and it requires significant resolution time to find optimal or even adequate solutions when dealing with large size instances. Thus, this paper proposes a dual island genetic algorithm consisting of a parallel cellular model and a parallel pseudo-model. This is a two-level parallelization highly consistent with the underlying architectures and is well suited for parallelizing inside or between GPUs and a multicore CPU. At the higher level, the efficiency of the island GA is improved by exploring new regions within the search space utilizing different methods. In the meantime, the cellular model keeps the population diversity by decentralization and the pseudo-model enhances the search ability by the complementary parent strategy at the lower level. To encourage the information sharing between islands, a penetration inspired migration policy is designed which sets the topology, the rate, the interval, and the strategy adaptively. Finally, the proposed method is tested on some large size flexible flow shop scheduling instances in comparison with other parallel algorithms. The computational results show that it not only can obtain competitive results but also reduces execution time.

Comparing the speed and accuracy of approaches to betweenness centrality approximation

BackgroundMany algorithms require doing a large number of betweenness centrality calculations quickly, and accommodating this need is an active open research area. There are many different ideas and approaches to speeding up these calculations, and it is difficult to know which approach will work best in practical situations.MethodsThe current study attempts to judge performance of betweenness centrality approximation algorithms by running them under conditions that practitioners are likely to experience. For several approaches to approximation, we run two tests, clustering and immunization, on identical hardware, along with a process to determine appropriate parameters. This allows an across-the-board comparison of techniques based on the dimensions of speed and accuracy of results.ResultsOverall, the speed of betweenness centrality can be reduced several orders of magnitude by using approximation algorithms. We find that the speeds of individual algorithms can vary widely based on input parameters. The fastest algorithms utilize parallelism, either in the form of multi-core processing or GPUs. Interestingly, getting fast results does not require an expensive GPU.ConclusionsThe methodology presented here can guide the selection of a betweenness centrality approximation algorithm depending on a practitioner’s needs and can also be used to compare new methods to existing ones.

Fair Allocation of Heterogeneous and InterchangeableResources

Motivated by the proliferation of heterogeneous processors such as multi-core CPUs, GPUs, TPUs, and other accelerators for machine learning, we formulate a novel multiinterchangeable resource allocation (MIRA) problem where some resources are interchangeable. The challenge is how to allocate interchangeable resources to users in a sharing system while maintaining desirable properties such as sharing incentive, Pareto efficiency, and envy-freeness. In this paper, we first show that existing algorithms, including the Dominant Resource Fairness used in production systems, fail to provide these properties for interchangeable resources. Then we characterize the tradeoff between performance and strategyproofness, and design the Budget-based (BUD) algorithm, which preserves Pareto efficiency, sharing incentive and envyfreeness while providing better performance over currently used algorithms.

Real-Time Simulation and Optimization of Elastic Aircraft Vehicle Based on Multi-GPU Workstation

Modern aircraft such as missile and rocket, due to the large slenderness ratio of slender body vehicles, the influence of elastic deformation and vibration on navigation, guidance, and engine modules in simulation can not be ignored. For the problems of slow calculation speed and incapability of real-time simulation for time-domain simulation, by analyzing the time proportion of each calculation step under different computing scale, the dynamic parallel construction of octree is used to represent the aerodynamic parameter table under the environment of single and multi GPU. Meanwhile, an innovative parallel algorithm of element stiffness matrix based on finite element model is designed in GPU architecture. Accordingly, the optimized performance is enhanced through the adaptive hardware resources and rational use of shared memory. Furthermore, A multi-threaded asynchronous framework based on task queue and thread pool is proposed to realize the parallel task calculation with different granularities. The numerical result shows that the acceleration ratio of about 20 times in the single GPU condition can be obtained, and the acceleration ratio of at least 30 times can be obtained by the parallel computing of dual GPUs, enabling the real-time simulation of the flexible aircraft with 1200 elements within 20ms.

Modeling Direct Transmission Diseases Using Parallel Bitstring Agent-Based Models

Agent-based models (ABMs) are gaining importance over traditional epidemiological modeling due to advances in computing technology and catalyzed by the need for detailed epidemiological analysis of emergent diseases. Unfortunately, the advantages of ABMs are realized at the cost of significantly large execution times and high memory consumption for large-scale simulations. To address the memory issue, we designed and implemented an ABM using an innovative feature: the bitstring approach, in which the attributes of each agent are represented by an array of bits instead using traditional data structures. To cope with the high computational demands, we developed a parallel version of model aiming multicore CPUs and GPUs architectures using Thrust parallel algorithms library. The results of our model were validated comparing them with data of a spread of Influenza A in the Cascavel City, South Brazil, occurred in 2009. The model presented good qualitative results and an excellent performance on GPUs. The application of bitstring technique is proved to be relevant in economy of memory, allowing to store the same attributes using 41% less memory space and improving the data copy time between CPU and GPU up to 52%.

Finite size effects in active microrheology in colloids

Active microrheology has emerged in recent years as a new technique to probe microscopically the mechanical properties of materials, particularly, viscoelastic ones. In this technique, a colloidal tracer is pulled through the material, and its dynamics is monitored. The interpretation of results usually relies on the Stokes–Einstein approximation, which is valid for a continuous medium in equilibrium. In this work, we have studied with simulations a suspension of quasi-hard colloidal spheres, where a large tracer is pulled by a constant force. The Navier–Stokes equation for a continuous bath predicts important finite size effects, decaying as the inverse box size, which require simulations of different systems to extract the microviscosity of a bulk system. A strategy to optimize the scheduling of the simulation tasks on a multi GPU–CPU cluster based on the adaptation of a genetic algorithm is presented here, and used to study the effect of different conditions on the friction experienced by the tracer (adding the tracer volume to the total system volume, fixing the center of mass of the system, varying the fluid friction coefficient and tracer size). It is observed that the theoretical prediction is not followed, but deviations are observed for large systems in all cases. These are attributed to the finite size of the bath particles, and the intrinsic dynamics of colloidal systems, as shown by the analysis of the velocity profile in the bath.

Design and Implementation of Adaptive SpMV Library for Multicore and Many-Core Architecture

Sparse matrix vector multiplication (SpMV) is an important computational kernel in traditional high-performance computing and emerging data-intensive applications. Previous SpMV libraries are optimized by either application-specific or architecture-specific approaches but present difficulties for use in real applications. In this work, we develop an auto-tuning system (SMATER) to bridge the gap between specific optimizations and general-purpose use. SMATER provides programmers a unified interface based on the compressed sparse row (CSR) sparse matrix format by implicitly choosing the best format and fastest implementation for any input sparse matrix during runtime. SMATER leverages a machine-learning model and retargetable back-end library to quickly predict the optimal combination. Performance parameters are extracted from 2,386 matrices in the SuiteSparse matrix collection. The experiments show that SMATER achieves good performance (up to 10 times that of the Intel Math Kernel Library (MKL) on Intel E5-2680 v3) while being portable on state-of-the-art x86 multicore processors, NVIDIA GPUs, and Intel Xeon Phi accelerators. Compared with the Intel MKL library, SMATER runs faster by more than 2.5 times on average. We further demonstrate its adaptivity in an algebraic multigrid solver from the Hypre library and report greater than 20% performance improvement.

A survey on techniques for cooperative CPU-GPU computing

Graphical Processing Unit provides massive parallelism due to the presence of hundreds of cores. Usage of GPUs for general purpose computation (GPGPU) has resulted in execution speedup and energy efficiency. In addition, the modern CPUs also possess multiple cores, with enormous computational power. In general, the current programming frameworks for CPU-GPU heterogeneous computing system do not facilitate the efficient utilization of computational resources so as to further improve the performance and reduce the energy consumption. Several researches have been carried out to improve the resource utilization and reduce the energy consumption of heterogeneous systems by cooperatively performing the computation on both multicore CPUs and GPUs. In this survey paper we review the various techniques available for CPU-GPU cooperative computing.

Scanner

A growing number of visual computing applications depend on the analysis of large video collections. The challenge is that scaling applications to operate on these datasets requires efficient systems for pixel data access and parallel processing across large numbers of machines. Few programmers have the capability to operate efficiently at these scales, limiting the field's ability to explore new applications that leverage big video data. In response, we have created Scanner, a system for productive and efficient video analysis at scale. Scanner organizes video collections as tables in a data store optimized for sampling frames from compressed video, and executes pixel processing computations, expressed as dataflow graphs, on these frames. Scanner schedules video analysis applications expressed using these abstractions onto heterogeneous throughput computing hardware, such as multi-core CPUs, GPUs, and media processing ASICs, for high-throughput pixel processing. We demonstrate the productivity of Scanner by authoring a variety of video processing applications including the synthesis of stereo VR video streams from multi-camera rigs, markerless 3D human pose reconstruction from video, and data-mining big video datasets such as hundreds of feature-length films or over 70,000 hours of TV news. These applications achieve near-expert performance on a single machine and scale efficiently to hundreds of machines, enabling formerly long-running big video data analysis tasks to be carried out in minutes to hours.

Generating custom code for efficient query execution on heterogeneous processors

Processor manufacturers build increasingly specialized processors to mitigate the effects of the power wall in order to deliver improved performance. Currently, database engines have to be manually optimized for each processor which is a costly and error- prone process. In this paper, we propose concepts to adapt to and to exploit the performance enhancements of modern processors automatically. Our core idea is to create processor-specific code variants and to learn a well-performing code variant for each processor. These code variants leverage various parallelization strategies and apply both generic- and processor-specific code transformations. Our experimental results show that the performance of code variants may diverge up to two orders of magnitude. In order to achieve peak performance, we generate custom code for each processor. We show that our approach finds an efficient custom code variant for multi-core CPUs, GPUs, and MICs.

Improving the performance and energy of Non-Dominated Sorting for evolutionary multiobjective optimization on GPU/CPU platforms

Non-Dominated Sorting (NDS) is the most time-consuming procedure used in the majority of evolutionary multiobjective optimization algorithms that are based on Pareto dominance ranking without regard to the computation time of the objective functions. It can be accelerated by the exploitation of its parallelism on High Performance Computing systems, that provide heterogeneous processing units, such as multicore processors and GPUs. The optimization of energy efficiency of such systems is a challenge in scientific computation since it depends on the kind of processing which is performed. Our interest is to solve NDS in an efficient way concerning both runtime and energy consumption. In literature, performance improvement has been extensively studied. Recently, a sequential Best Order Sort (BOS) algorithm for NDS has been introduced as one of the most efficient one in terms of practical performance. This work is focused on the acceleration of the NDS on modern architectures. Two efficient parallel NDS algorithms based on Best Order Sort, are introduced, MC-BOS and GPU-BOS. Both algorithms start with the fast sorting of population by objectives. MC-BOS computes in parallel the analysis of the population by objectives on the multicore processors. GPU-BOS is based on the principles of Best Order Sort, with a new scheme designed to harness the massive parallelism provided by GPUs. A wide experimental study of both algorithms on several kinds of CPU and GPU platforms has been carried out. Runtime and energy consumption are analysed to identify the best platform/algorithm of the parallel NDS for every particular population size. The analysis of obtained results defines criteria to help the user when selecting the optimal parallel version/platform for particular dimensions of NDS. The experimental results show that the new parallel NDS algorithms overcome the sequential Best Order Sort in terms of the performance and energy efficiency in relevant factors.

Accelerating subset sum and lattice based public-key cryptosystems with multi-core CPUs and GPUs

Post-quantum cryptosystems based on subset sum and lattice problems have gained much attention from researchers due to their simple construction, their resistance to quantum attacks, the new potential applications they provide, and above all, the mathematical security proofs that rigorously relate them to computational hard problems. However, the computational complexity of these cryptosystems is still high compared to classic number-theoretical ones, which may impede their adoption on a large scale. We studied the performance of three public-key cryptosystems based on subset sum, learning with errors and ring learning with errors problems. We provide a systematic study for choosing their parameters to guarantee sufficient security levels and detail an asymptotic comparison between them in terms of storage and running time complexities. We accelerate the running time of these cryptosystems by exploiting the inherent parallelism in computations through a GPGPU-based parallel implementation. The cryptosystems are implemented using C++ on Intel(R) Xeon(R) multi-core 64-bit processors machine with CUDA-enabled Tesla K80 GPUs. The parallel implementation is based on OpenCL framework and can run on arbitrary hardware platform accelerators with minor changes. Several optimizations and efficient algorithms were used to compute the core operations in each cryptosystem to achieve optimum performance. The ring learning with errors based cryptosystem showed the best performance while the Subset Sum cryptosystem showed the highest speedup gain for the encryption primitive.

Optimized sparse Cholesky factorization on hybrid multicore architectures

We present techniques for supernodal sparse Cholesky factorization on a hybrid multicore platform consisting of a multicore CPU and GPU. The techniques are the subtree algorithm, pipelining and multithreading. The subtree algorithm [15] minimizes PCIe transmissions by storing an entire branch of the elimination tree in the GPU memory (the elimination tree is a tree data structure describing the workflow of the factorization), and also reduces the total kernel launch time by launching BLAS kernels in batches. The pipelining technique overlaps the execution of GPU kernels and PCIe data transfers. The multithreading technique [17] creates multiple threads for both the CPU and the GPU, to utilize concurrency of the elimination tree. Our experimental results on a platform consisting of an Intel multicore processor along with an Nvidia GPU indicate a significant improvement in performance and energy over CHOLMOD (SuiteSparse 4.5.3), a sparse algorithm, after these techniques are applied.

FID-sketch: an accurate sketch to store frequencies in data streams

Sketches are being extensively used in a large number of real world applications to estimate frequencies of data items. Due to the unprecedented increase in the amount of Internet data and a relatively slower increase in the size of on-chip memories, existing sketches are becoming increasingly unable to keep the accuracy of the frequency estimates at an acceptable level. In this paper, we design a new sketch, called FID-sketch, that has a significantly higher accuracy and a much smaller on-chip memory footprint compared to the existing sketches. The key intuition behind the design of the FID-sketch is that before inserting an item, unlike prior sketches, it first estimates the current value of the frequency of that item stored in the sketch, and then increments as few counters as possible instead of incrementing a pre-determined fixed number of counters. We carried out extensive experiments to evaluate and compare the performance of FID-sketch with existing sketches on multi-core CPU and GPU platforms. Our experimental results show that our FID-sketch significantly outperforms the state-of-the-art with 36.7 times lower relative error. We have released the source code of our proposed sketch and other related sketches that we implemented at Github [21].

Parallel scalability and efficiency of vortex particle method for aeroelasticity analysis of bluff bodies

This paper presents an analysis of the scalability and efficiency of a simulation framework based on the vortex particle method. The code is applied for the numerical aerodynamic analysis of line-like structures. The numerical code runs on multicore CPU and GPU architectures using OpenCL framework. The focus of this paper is the analysis of the parallel efficiency and scalability of the method being applied to an engineering test case, specifically the aeroelastic response of a long-span bridge girder at the construction stage. The target is to assess the optimal configuration and the required computer architecture, such that it becomes feasible to efficiently utilise the method within the computational resources available for a regular engineering office. The simulations and the scalability analysis are performed on a regular gaming type computer.