Multi-channel Field-effect Transistors Research Articles

Electron beam lithography and dimensional metrology for fin and nanowire devices on Ge, SiGe and GeOI substrates

Until now there is no systematic study on the effect of the substrate type on the hydrogen silsesquioxane (HSQ) electron beam lithography (EBL) patterning process. We investigate arrays of line structures with varying width and spacing, starting at 10 nm, exposed at varying dose, and developed by salty NaOH and TMAH developers on group IV semiconductor substrates. We demonstrate that the HSQ EBL process on Ge is much more limited in achieving the smallest obtainable features, having optimal uniformity and fidelity, in comparison to Si. Monte-Carlo simulations of the e-beam/substrate interactions for “pure” Si and Ge substrates, and varying content Ge/Si epitaxial layers on Si, suggest that the limitations seen are directly linked to back-scattered electron (BSE) generation. As predicted by the simulations and shown experimentally, improved fidelity and resolution of the features can be achieved by minimizing the (BSE) generation coming from the Ge contribution in the substartes. Finally, from a metrology perspective, it is demonstrated that although line patterns may appear resolved in SEM images, the variation in the brightness across neighbouring lines is a key parameter in understanding the resist clearance between lines, that will affect the next etching step for pattern transfer onto the underlying substrate. These results are important for patterning high-density line structures and nano-device engineering as required for realising state-of-the art laterally stacked group IV multi-channel field effect transistors (FETs).

Performance Analysis of Incorporating a Buried Metal Layer in a Junction-Less Multi-Channel Field Effect Transistor

Performance Analysis of Incorporating a Buried Metal Layer in a Junction-Less Multi-Channel Field Effect Transistor

Future Trends for Carbon Nanotube Transistors in Sensing and Transmitting Data

Recently, the printing technologies for mass producing flexible and elastic electronics might significantly broaden the range of uses for electronics and transform the way people think about them. This document offers a summary of the most current research in this area. The structure that allows for the transmission of data involves the transfer of information from one channel to another by way of a very flexible film model transistor assisted by an integrated circuit procedure. The semiconductor industry makes extensive use of wall-based carbon nanotubes for the purpose of developing models with improved efficiency. This study provides a comprehensive explanation of single and multi-channel field-effect transistors, both of which are used for the process of data transmission using flexible carbon nanotube transistors in applications such as hearing aid equipment. This research work go through all the recent tweaks to the printing process for sensing and transmitting data from one to another source. All of these modifications are ideal for the mass-production of stretchy and flexible electronics.

SWCNT 다중채널 FET용 표면 프로그램된 APTES와 OTS 패턴을 이용한 공정에 대한 연구

In this paper, we have investigated a selective assembly method of single-walled carbon nanotubes (SWCNTs) on a silicon substrate using only photolithographic process and then proposed a fabrication method of field effect transistors (FETs) using SWCNT-based patterns. The aminopropylethoxysilane (APTES) patterns, which are formed for positively charged surface molecular patterns, are utilized to assemble and align millions of SWCNTs and we can more effectively assemble on a silicon (Si) surface using this method than assembly processes using only the 1-octadecyltrichlorosilane (OTS). We investigated a selective assembly method of SWCNTs on a Si surface using surface-programmed APTES and OTS patterns and then a fabrication method of FETs. photoresist(PR) patterns were made using photolithographic process on the silicon dioxide (SiO2) grown Si substrate and the substrate was placed in the OTS solution (1:500 v/v in anhydrous hexane) to cover the bare SiO2 regions. After removing the PR, the substrate was placed in APTES solution to backfill the remaining SiO2 area. This surface-programmed substrate was placed into a SWCNT solution dispersed in dichlorobenzene. SWCNTs were attracted toward the positively charged molecular regions, and aligned along the APTES patterns. On the contrary, SWCNT were not assembled on the OTS patterns. In this process, positively charged surface molecular patterns are utilized to direct the assembly of negatively charged SWCNT on SiO2. As a result, the selectively assembled SWCNT channels can be obtained between two electrodes(source and drain electrodes). Finally, we can successfully fabricate SWCNT-based multi-channel FETs by using our self-assembled monolayer method.

Contact printing of horizontally aligned Zn2GeO4and In2Ge2O7nanowire arrays for multi-channel field-effect transistors and their photoresponse performances

The ternary oxides, Zn2GeO4 and In2Ge2O7 nanowires, are promising n-type semiconductors with outstanding transport properties for high performance electronic devices. By using the direct contact printing process, we reported the assembly of horizontally aligned Zn2GeO4 and In2Ge2O7 nanowire arrays to be used as building blocks for high performance multi-channel field-effect transistors. The as-fabricated multi-channel transistors exhibited higher voltage stability and repeatability than their single nanowire based counterparts. The effective mobilities of the multi-channel field-effect transistors were calculated to be 25.44 cm2 V−1 s−1 and 11.9 cm2 V−1 s−1, comparable to the single-channel FETs. The as-fabricated multi-channel transistors were also used as high performance photodetectors, exhibited a high sensitivity to ultraviolet light illumination with a photoconductive gain and quantum efficiency as high as 1.034 × 105 and 1.032 × 107% for Zn2GeO4 nanowires and 2.58 × 105 and 2.617 × 107% for In2Ge2O7 nanowires.

Transport Characteristics of Multichannel Transistors Made from Densely Aligned Sub-10 nm Half-Pitch Graphene Nanoribbons

Densely aligned sub-10 nm graphene nanoribbons are desirable for scale-up applications in nanoelectronics. We implemented directed self-assembly of block-copolymers in combination with nanoimprint lithography to pattern sub-10 nm half-pitch nanoribbons over large areas. These graphene nanoribbons have the highest density and uniformity to date. Multichannel field-effect transistors were made from such nanoribbons, and the transport characteristics of transistors were studied. Our work indicates that a large ribbon-to-ribbon width variation in a multichannel FET can lead to nonsynchronized switching characters of multiple graphene channels and thus a poor ON/OFF current ratio. Through process optimization, we have created 8 nm half-pitch graphene nanoribbons with the minimal ribbon-to-ribbon width variation of ∼2.4 nm (3σ value). The corresponding transistors exhibit an ON/OFF current ratio >10, which is among the highest values ever reported for transistors consisting of densely arranged graphene nanoribbons. This work provides important insights for optimizing the uniformity and transport properties of lithographically patterned graphene nanostructures. In addition, the presented fabrication route could be further developed for the scalable nanomanufacturing of graphene-based nanoelectronic devices over large areas.

Influence of source/drain formation process on resistance and effective mobility for scaled multi-channel MOSFET

The influence of doping process in selective epitaxial growth of source/drain, for vertically aligned three-dimensional multi-channel field-effect transistors (MCFETs), is examined. We show that the electrical performance of short devices strongly depends on the optimization of source drain regions. In situ doped epitaxial process results in a significant reduction in the series resistance. A further improvement, for both n- and p-MCFETs, is obtained by combination in situ doping with ion implantation. The effective mobility, however, is degraded by additional Coulomb scattering due to dopant diffusion into the channel. The detailed mobility analysis reveals the possibility for future process optimization based on the tight control of the activation annealing step during the source/drain formation.

Size-dependent properties of ballistic silicon nanowire field effect transistors

A study on size-dependent subband structures of silicon nanowires (SiNWs) aligned along [100] direction, ranging from 0.77 to 2.69 nm in width, is performed by the first-principles calculation. Combined with a compact model adopting Landauer’s formula, on-currents of ballistic SiNW field effect transistors (FETs) are estimated and assessment of size-dependent performance is conducted. Size-dependent injection velocity strongly depends on Fermi level measured from the conduction band edge when carriers are degenerate. It is also supposed that the Fermi level has a peak value at a certain wire width. Despite variation in the size-dependent Fermi level and injection velocity, large SiNW FETs show large on-currents owing to their larger gate capacitances resulting from longer periphery. The on-current in the case of a multichannel SiNW FET reveals that size-dependent subband structures of nanowires have a serious effect on performance. As the results, although the normalized on-current decreases with decrease in wire width in the assessed multichannel FETs because both the saturation velocities and the normalized capacitances decrease, there can be a maximum in the normalized on-current in a larger wire owing to the maximized Fermi level and injection velocity.

Effect of Surface Passivation on Dielectrophoresis-Prepared Multi-Channel ZnO Nanowire Field Effect Transistor (FETs)

We report on the effect of surface passivation on the electrical characteristics of multi-channel ZnO nanowire field-effect transistors (FETs). Surface passivation was performed using a SiO2 layer on ZnO nanowires. Multi-channel FETs were prepared by assembling as synthesized ZnO nanowires on a SiO2/Si substrate using an alternating current (AC) dielectrophoresis (DEP) technique. We observed that surface passivation with a SiO2 layer on ZnO nanowires was significantly affected by electrical characteristics of multi-channel ZnO nanowire FETs such as the threshold voltage and transconductance.

Multi-Channel Field-Effect Transistor (MCFET)—Part I: Electrical Performance and Current Gain Analysis

Multi-Channel Field-Effect Transistor (MCFET) structures with ultralow I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OFF</sub> (16 pA/mum) and high I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> (N: 2.27 mA/mum and P: 1.32 mA/mum) currents are obtained on silicon on insulator (SOI) with a high-kappa/metal gate stack, satisfying both low-standby-power and high-performance requirements. The experimental current gain of the MCFET structure is compared with that of an optimized planar FD-SOI reference with the same high-kappa/metal gate stack and is quantitatively explained by an analytical model. Transport properties are investigated, and the specific MCFET electrostatic properties are evidenced, in particular a higher V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Dsat</sub> for MCFETs compared with the planar reference. Finally, through 3-D numerical simulations correlated with specific characterizations, the influence of the channel width on the electrical performance is analyzed. For narrow devices, the parasitic bottom channel increases the total drain current of the MCFET structure without degrading the electrostatic integrity.

Multichannel Field-Effect Transistor (MCFET)—Part II: Analysis of Gate Stack and Series Resistance Influence on the MCFET Performance

Three-dimensional multi-channel field-effect transistor (MCFET) gate stack and series resistance are investigated and optimized by specifically developed integration processes, characterization methods, and numerical simulations. First, the impact of a TiN/HfO2 gate stack on embedded-gate MCFET structure performance is studied. Both TiN/SiO2 and N+poly-Si/SiO2 gate stacks were introduced in the MCFET to compare the carrier mobility behavior (300 K down to 20 K), the gate leakage current, and the negative bias temperature instability. The obtained electrical data are then compared with a planar FD-SOI reference, highlighting some specific challenges linked to the introduction of a high- kappa/metal gate stack in embedded cavities. On the other hand, it is shown how the series resistance is intrinsically increased by the 3-D configuration. We also show how this increase can be attenuated significantly by optimizing the source/drain (S/D) shape, the implantation conditions, and the S/D silicide position.

Carbon Nanotube Multi-Channeled Field-Effect Transistors

Field-effect transistors (FETs) with multiple channels of single-wall carbon nanotubes (SWCNTs) have been constructed. SWCNT channels of the FETs are dispersedly aligned between the source and the drain by electric-field manipulation of surface decorated SWCNTs. The obtained multichanneled FETs not only can meet the requirement of large output current and high transconductance, but also manifested good reliability and applicability. It is found that the transconductance of the multi-channel FET has an almost linear dependency on the SWCNT channel number, which opens up a promising way to tune the transconductance of FETs by controlling the channel number.

Field-effect transistors with multiple channels constructed by carbon nanotubes

Single-wall carbon nanotubes (SWNTs) pre-decorated with functional molecules are directly aligned in the AC electric field, which makes SWNTs parallelly bridge the source and drain electrodes and act as the multiple conduction channels of the field-effect transistor (FET). The method avoids the mutual tanglement of SWNTs and makes them align between the source and drain electrodes abreast and dispersedly. It is indicated that aligning SWNTs in the high-volatility solvents can decrease the contaminant around the electrodes and has a function to purify the raw SWNTs. The obtained multi-channel FET not only takes on a high transconductance, but also holds the good reliability and stability.

Effect of the oxide thickness on the operation speed of a field-effect transistor in terms of the carrier tunneling rate

A parameter characterizing the dependence of the velocity of electron tunneling through an oxide layer on the layer thickness is introduced. This parameter can be used to study the operation speed of multi-channel field-effect transistors with control and floating gates. Estimates of the proposed characteristic quantity for the most typical experimental situations are obtained.

Multi-channel field-effect transistor theory and experiment

Experimental and theoretical results are presented on a planar, silicon multi-channel field-effect transistor with vertical channel arrangement. This includes: the theory of a field-effect transistor with short channels, which achieves drain current saturation owing to the limiting velocity of charge carriers; experimental results on the construction and electrical evaluation of a 100 and 1141 channel device; and correlation of electrical results with the device physics and structure. The limitations of the device structures investigated are assessed with respect to frequency and power capability, and extrapolated to improved device structures of the near future by employing refined photolithographic masking and new silicon technologies not presently available.

Transition from pentode- to triode-like characteristics in field effect transistors

It is shown with the use of the Geurst theory that field effect transistors should exhibit a transition from pentode-like to triode-like characteristics with increasing drain bias, corresponding to the approach of the pinch-off point to the source and to space-charge-limited injection from the source. The transition point is markedly geometry-dependent and occurs at lower voltages the smaller the ratio of channel length/channel (or insulator)_thickness. The theoretical results permit clarification of the origin of the widely diverse characteristics observed in multi-channel field effect transistors.