Multichannel ASIC Research Articles

Development of the Beam Conditions Monitoring Prime system for beam abort and luminosity monitoring in ATLAS based on a segmented polycrystalline CVD diamond system and dedicated front-end ASIC

The High Luminosity upgrade of Large Hadron Collider (HL-LHC) will increase the LHC luminosity and with it the density of particles on the detector by an order of magnitude. For protecting the inner silicon detectors of the ATLAS experiment and for monitoring the delivered luminosity, a radiation hard beam monitor was developed based on polycrystalline Chemical Vapor Deposition (pCVD) diamond detectors and a new dedicated rad-hard front-end ASIC. Due to the large range of particle flux through the detector, flexibility is very important. To satisfy the requirements imposed by the HL-LHC, our solution is based on segmenting diamond sensors into devices of varying size and reading them out with new multichannel readout ASICs divided into two independent parts — each of them serving one of the tasks of the system. This paper describes the system design including detectors, electronics, mechanics and services and presents preliminary results from the most recent detectors fabricated, using our prototype ASIC with data from beam tests at CERN.

Ultra-low power 10-bit 50–90 MSps SAR ADCs in 65 nm CMOS for multi-channel ASICs

The design and measurement results of ultra-low power, fast 10-bit Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC) prototypes in 65 nm CMOS technology are presented. Eight prototype ADCs were designed using two different switching schemes of capacitive Digital-to-Analog Converter (DAC), based on MIM or MOM capacitors, and controlled by standard or low-power SAR logic. The layout of each ADC prototype is drawn in 60 μm pitch to make it ready for multi-channel implementation. A series of measurements have been made confirming that all prototypes are fully functional, and six of them achieve very good quantitative performance. Five out of eight ADCs show both integral (INL) and differential (DNL) nonlinearity errors below 1 LSB. In dynamic measurements performed at 0.1 Nyquist input frequency, the effective number of bits (ENOB) between 8.9–9.3 was obtained for different ADC prototypes. Standard ADC versions work up to 80–90 MSps with ENOB between 8.9–9.2 bits at the highest sampling rate, while the low-power versions work up to above 50 MSps with ENOB around 9.3 bits at 40 MSps. The power consumption is linear with the sample rate and at 40 MSps it is around 400 μW for the low-power ADCs and just over 500 μW for the standard ADCs. At 80 MSps the standard ADCs consume about 1 mW.

A SiPM multichannel ASIC for high Resolution Cherenkov Telescopes (SMART) developed for the pSCT camera telescope

A SiPM multichannel ASIC for high Resolution Cherenkov Telescopes (SMART) developed for the pSCT camera telescope

Quality control tests on the new front-end electronics for the Schwarzschild–Couder Telescope

One of the proposed Medium-Sized Telescopes for the Cherenkov Telescope Array is the dual mirror optics Schwarzschild–Couder Telescope (SCT). The prototype SCT camera is currently equipped with 24 SiPM modules each one made of 64 pixels. The upgrade of the current camera is in progress, with the aim of fully equipping the 177 SiPM modules. A new front-end electronics is being developed and tested in order to improve the noise performance and match CTA requirements. In this process, 11328 SiPMs and the related electronics will be tested in the laboratories before the assembly on the telescope camera. The SiPM Multichannel ASIC for high Resolutions Cherenkov Telescope (SMART) has been developed by INFN to amplify the SiPM signals to be digitized and inserted in the trigger logic based on the TeV Array with GSa/s sampling and Experimental Trigger Application Specific Integrated Circuit (TARGET ASICs). An experimental setup has been devised to test about 750 SMART, which will be used to equip the full camera of the prototype SCT. Each SMART was tested for proper operation in response to a laser pulse. In this contribution we present a detailed scheme of the test bench and the first results obtained on the quality control measurements.

Low-Noise Analog Channel for the Readout of the Si(Li) Detector of the GAPS Experiment

This work is focused on the design and the experimental characterization of an analog channel developed for the readout of lithium-drifted silicon detectors of the General AntiParticle Spectrometer (GAPS) experiment aimed at the search for dark matter. The instrument is designed for the identification of antideuteron particles from cosmic rays during an Antarctic balloon mission scheduled for late 2022. A low-noise analog front-end, featuring a dynamic signal compression to comply with the wide input range, has been designed in commercial 180-nm CMOS technology. The channel was fabricated in 2018 and is the first building block toward the development of a multichannel readout ASIC. The article will provide a description of the design criteria, the architecture of the channel, and a summary of the results of the experimental characterization.

A serial-timing multi-channel CMOS charge readout ASIC for X-ray detectors

A serial-timing multi-channel CMOS charge readout ASIC for X-ray detectors

OMEGA SiPM readout ASICs

The paper describes various multi-channel ASICs designed by OMEGA laboratory and WEEROC company to readout SiPM or MPPC-based detectors used in particle physics or astrophysics experiments.

A single ion discriminator ASIC prototype for particle therapy applications

In the framework of the development of future advanced treatment modalities in charged particle therapy, the use of silicon sensors is an appealing alternative to gas ionization chambers commonly used for beam monitoring. A prototype of a device, based on Low-Gain Avalanche Diode (LGAD) sensors with 50μm thickness, is being developed to discriminate and count single beam particles. This paper describes the design and characterization of ABACUS, an innovative multi-channel ASIC prototype for LGAD readout, based on a fast amplifier with self-reset capabilities. The design goals aim at detecting charge pulses in a wide range, from 4 fC to 150 fC, up to 70 MHz instantaneous rates, with a dead time of about 10 ns or less and efficiency larger than 98%. The characterization results indicate that even at the lowest input charge the signal-to-noise ratio is 15, high enough to keep full efficiency and preventing fake counts from the electronics noise. The dead time was found to be in the range between 5 ns and 10 ns, allowing to reach a full counting efficiency up to instantaneous rates of 70 MHz or larger, depending on the input charge.

A multichannel front-end readout ASIC for picosecond time resolution systems based on thin UFSD

This work presents FAST, a multichannel readout ASIC designed to measure the time of arrival of MIP particles in Ultra-Fast Silicon Detectors (UFSD) with a time resolution of about 30 ps. The FAST ASIC is oriented to future High Energy Physics experiments, where high time resolution is exploited to mitigate pile-up effects, and more generally, to those applications that require accurate Time-of-Flight Silicon systems with low power consumption. The prototype has been designed in 110 nm CMOS technology, in three different flavors of front-end architecture. Each flavor is implemented in a different 20-channel ASIC. For all flavors, the power consumption of the front-end is 1.2 mW/channel. The three flavors of FAST are described in the paper, together with the simulation showing the timing performance of FAST coupled to different sensors geometries.

A precision luminometer for future linear collider experiments

The FCAL collaboration develops the technologies of compact and fast calorimeters to measure the luminosity at Linear Collider experiments both with high precision using small angle Bhabha scattering, and bunch-by-bunch using beamstrahlung pairs. Beside the luminosity measurement, the capability of detecting high energy electrons at low angles is important for many search experiments. A small Molière radius facilitates the measurement of Bhabha events in the presence of background and allows the detection of single high energy electrons on top of the widely spread background of beamstrahlung. A multi-plane prototype of a compact precision luminometer was studied in an electron beam with energies between 1 and 5 GeV at DESY. The results for the longitudinal and the transverse shower profiles are compared with Geant4 simulations of the setup. Very good agreement was obtained. The effective Molière radius of the prototype was determined. Again, very good agreement between data and Monte Carlo simulations was found. The value of the Molière radius approached the technological limit. A dedicated multi-channel ultra-low power readout ASIC is under development in 130 nm CMOS, comprising an analogue front-end and fast 10-bit ADC in each channel, followed by fast serialization and data transmission. In addition, an ASIC with a dual readout scheme allowing for a fast feedback to the accelerator and simultaneous data taking and calibration is under development. The paper summarizes the results on design optimization, beam-tests and the status of the readout ASICs.

Validation and Performance Assessment of a Preclinical SiPM-Based SPECT/MRI Insert

A preclinical insert for small animal simultaneous SPECT and MR imaging, in particular for imaging mouse brains, is presented. It consists of ten static magnetic resonance imaging (MRI)-compatible gamma cameras based on tiles of silicon photomultipliers readout by a multichannel ASIC and coupled to 5 cm $\boldsymbol \times $ 5 cm CsI(Tl) scintillators and to an MRI-compatible multipinhole collimator. Calibration and image reconstruction algorithm are illustrated. Mutual compatibility is demonstrated along with imaging performance that is comparable with other non-MR micro-SPECT systems: 0.9 mm tomographic spatial resolution across a transverse field of view of 15.6 mm, 12% energy resolution (at 140 keV), and 1105 cps/MBq sensitivity. Experimental results with phantoms (glass capillaries of 290 $ \mu \text{m}$ diameter and a mini Derenzo) are presented.

Experimental test and characterization of BASIC64, a new mixed-signal front-end ASIC for SiPM detectors

BASIC64 is a new multichannel front-end ASIC for Silicon photomultiplier detectors used in PET systems. The preamplifier input resistance is ∼ 50 Ω , low enough not to further affect the slope of incoming current pulses, already plagued by the presence of stray series inductance . For each channel, the signals generated by the detector follow two parallel processing paths, respectively for timing and energy measurements. The results of experimental test and characterization for timing accuracy and gain linearity are presented and confirm that BASIC64 is suitable for PET applications. • Design and characterization of a SiPM readout front-end with a 50 W input resistance. • Linearity and jitter evaluation in many operative conditions. • The ASIC is suitable for PET applications.

DIET: a multi-channel SiPM readout ASIC for TOF-PET with individual energy and timing digitizer

Monolithic scintillator detectors readout by silicon photomultiplier arrays can achieve favorable timing and spatial resolution in three dimensions and hence may significantly improve the sensitivity of PET and TOF-PET systems. This paper presents the development of a 64-channel SiPM readout ASIC, named DIET, with individual amplification and digitization of both energy and timing information. The chip performance such as input range and resolution were optimized for continuous LYSO crystal readout. The digitizer was implemented by a time-to-amplitude converter and a 10-bit Wilkinson type analog-to-digital converter. An automatic calibration method was proposed and implemented based on the timing distribution of SiPM dark counts. A prototype ASIC was fabricated in 0.18 μm CMOS process with the die area of 3 × 3 mm2. The chip was fully evaluated. For the energy measurement, the INL and noise was measured to be less than 0.6% and 0.88% respectively. For the timing measurement, the bin size of the time digitizer was measured to be 25 ps and the DNL of less than 0.45 LSB. The time resolution of 63.6 ps FWHM in single channel has been achieved for 20 p.e. signals at 0.5 p.e. threshold. The power consumption of the chip was less than 5 mW per channel. The chip was also tested with LYSO crystals (2 mm × 2 mm × 11 mm) coupled to SensL SiPMs after calibration with the dark counts. The energy resolution of 511 keV peak was measured to be 12.6% FWHM and the CRT of 334 ps FWHM was achieved.

An external control unit implemented for stimulator ASIC testing

This paper presents the design and development of an external control unit (ECU) for a stimulator ASIC testing purposes. The ECU consists of a graphical user interface (GUI) from the PC, a data transceiver and a power transmitter. The GUI was developed using MATLAB for stimulation data setup. The data transceiver was designed using hardware description language (HDL) Verilog code and was implemented in a Virtex-II Pro FPGA board. The overall stimulator ASIC design architecture and its operation for an epiretinal implant application are briefly explained to correlate with the ECU’s design requirements. The flexible multichannel stimulator ASIC was successfully fabricated in a 0.35μm AMS HVCMOS technology. Conducted simulation and measurement results on stimulation waveform generation, supply voltage compliance and external control of supply voltage adaptation validate the functionality of the designed ECU and the stimulator ASIC.

Latency study of the High Performance Time to Digital Converter for the ATLAS Muon Spectrometer trigger upgrade

The High Performance Time to Digital Converter (HPTDC), a multi-channel ASIC designed by the CERN Microelectronics group, has been proposed for the digitization of the thin-Resistive Plate Chambers (tRPC) in the ATLAS Muon Spectrometer Phase-1 upgrade project. These chambers, to be staged for higher luminosity LHC operation, will increase trigger acceptance and reduce or eliminate the fake muon trigger rates in the barrel-endcap transition region, corresponding to pseudo-rapidity range 1<|η|<1.3. Low level trigger candidates must be flagged within a maximum latency of 1075 ns, thus imposing stringent signal processing time performance requirements on the readout system in general, and on the digitization electronics in particular. This paper investigates the HPTDC signal latency performance based on a specially designed evaluation board coupled with an external FPGA evaluation board, when operated in triggerless mode, and under hit rate conditions expected in Phase-I. This hardware based study confirms previous simulations and demonstrates that the HPTDC in triggerless operation satisfies the digitization timing requirements in both leading edge and pair modes.

Integrated input protection against discharges for Micro Pattern Gas Detectors readout ASICs

Immunity against possible random discharges inside active detector volume of MPGDs is one of the key aspects that should be addressed in the design of the front-end electronics. This issue becomes particularly critical for systems with high channel counts and high density readout employing the front-end electronics built as multichannel ASICs implemented in modern CMOS technologies, for which the breakdown voltages are in the range of a few Volts. The paper presents the design of various input protection structures integrated in the ASIC manufactured in a 350 nm CMOS process and test results using an electrical circuit to mimic discharges in the detectors.

Development of the multichannel data processing ASIC design flow

In modern multichannel data processing digital systems the number of channels ranges from some hundred thousand to millions. The basis of the elemental base of these systems are ASICs. Their most important characteristics are performance, power consumption and occupied area. ASIC design is a time and labor consuming process. In order to improve performance and reduce the designing time it is proposed to supplement the standard design flow with an optimization stage of the channel parameters based on the most efficient use of chip area and power consumption.

Simulation of the High Performance Time to Digital Converter for the ATLAS Muon Spectrometer trigger upgrade

The ATLAS Muon Spectrometer endcap thin-Resistive Plate Chamber trigger project compliments the New Small Wheel endcap Phase-1 upgrade for higher luminosity LHC operation. These new trigger chambers, located in a high rate region of ATLAS, will improve overall trigger acceptance and reduce the fake muon trigger incidence. These chambers must generate a low level muon trigger to be delivered to a remote high level processor within a stringent latency requirement of 43 bunch crossings (1075 ns). To help meet this requirement the High Performance Time to Digital Converter (HPTDC), a multi-channel ASIC designed by CERN Microelectronics group, has been proposed for the digitization of the fast front end detector signals. This paper investigates the HPTDC performance in the context of the overall muon trigger latency, employing detailed behavioral Verilog simulations in which the latency in triggerless mode is measured for a range of configurations and under realistic hit rate conditions. The simulation results show that various HPTDC operational configurations, including leading edge and pair measurement modes can provide high efficiency (>98%) to capture and digitize hits within a time interval satisfying the Phase-1 latency tolerance.

A prototype scalable readout system for micro-pattern gas detectors**Supported by National Natural Science Foundation of China (11222552)

A scalable readout system (SRS) is designed to provide a general solution for different micro-pattern gas detectors in various applications. The system mainly consists of three kinds of modules: the ASIC card, the adapter card and the front-end card (FEC). The ASIC cards, mounted with particular ASIC chips, are designed for receiving detector signals. The adapter card is in charge of digitizing the output signals from several ASIC cards. The FEC, edged-mounted with the adapter, has field-programmable gate array (FPGA)-based reconfigurable logic and I/O interfaces, allowing users to choose different ASIC cards and adapters for different experiments, which expands the system to various applications. The FEC transfers data through Gigabit Ethernet protocol realized by a TCP processor (SiTCP) IP core in FPGA. By assembling a flexible number of FECs in parallel through Gigabit Ethernet, the readout system can be tailored to specific sizes to adapt to the experiment scales and readout requirements. In this paper, two kinds of multi-channel ASIC chip, VA140 and AGET, are applied to verify the scalability of this SRS architecture. Based on this VA140 or AGET SRS, one FEC covers 8 ASIC (VA140) cards handling 512 detector channels, or 4 ASIC (AGET) cards handling 256 detector channels, respectively. More FECs can be assembled in crates to handle thousands of detector channels.

Readout electronics for the silicon micro-strip detector of the ILD concept

Si-strips are the baseline for the Forward Tracker Detector (FTD) of the International Linear Detector (ILD). The main element of the front-end electronics is a multi-channel ASIC for self-triggered detection and processing of low level charge signals. The architecture used in this chip is very similar to the typical structure of a Si-strip readout system presented in previous works. Nevertheless, some design modifications have been included to reduce the Equivalent Noise Charge (ENC).