Multibit Digital-to-analog Converter Research Articles

Necessary and sufficient conditions for mismatch shaping in a general class of multibit dacs

Multibit digital-to-analog converters (DACs) are often constructed by combining several 1-bit DACs of equal or different weights in parallel. In such DACs, component mismatches give rise to signal dependent error that can be viewed as additive DAC noise. In some cases these DACs use dynamic element matching techniques to decorrelate the DAC mismatch noise from the input sequence and suppress its power in certain frequency bands. Such DACs are referred to as mismatch-shaping DACs and have been used widely as enabling components in state-of-the-art /spl Delta//spl Sigma/ data converters. Several different mismatch-shaping DAC topologies have been presented, but theoretical analyses have been scarce and no general unifying theory has been presented in the previously published literature. This paper presents such a unifying theory in the form of necessary and sufficient conditions for a multibit DAC to be a mismatch-shaping DAC and applies the conditions to evaluate the DAC noise generated by several of the previously published mismatch-shaping DACs and qualitatively compare their behavior.

A low-power 98-dB multibit audio DAC in a standard 3.3-V 0.35-μm CMOS technology

An oversampled digital-to-analog converter (DAC) is presented. The performance of this device has been achieved with a careful tradeoff with power consumption. A digital /spl Sigma//spl Delta/ modulator has been optimized for the 96-dB target. In the switched-capacitor reconstruction filter (SCF), the input structure is embedded in the feedback loop in order to reduce the output noise. The order of the SCF is three, larger than in competitive solutions, allowing to achieve a lower out-of-band noise. Finally, the differential-to-single-ended converter does not strongly limit the overall DAC channel performance. The device has been realized in a standard 3.3-V CMOS technology. With a 28-mW-per-channel power consumption the dynamic range is 98 dB, while the SNDR peak is 86 dB.

A low oversampling ratio 14-b 500-kHz ΔΣ ADC with a self-calibrated multibit DAC

Delta-sigma (/spl Delta//spl Sigma/) analog-to-digital converters (ADC's) rely on oversampling to achieve high-resolution. By applying multibit quantization to overcome stability limitations, a circuit topology with greatly reduced oversampling requirements is developed. A 14-bit 500-kHz /spl Delta//spl Sigma/ ADC is described that uses an oversampling ratio of only 16. A fourth-order embedded modulator, four-bit quantizer, and self-calibrated digital-to-analog converter (DAC) are used to achieve this performance. Although the high-order embedded architecture was previously thought to be unstable, it is shown that with proper design, a robust system can be obtained. Circuit design and implementation in a 1.2-/spl mu/m CMOS process are presented. Experimental results give a dynamic range of 84 dB with a sampling rate of 8 MHz and oversampling ratio of 16. This is the lowest oversampling ratio for this resolution and bandwidth achieved to date.