Multibit Digital-to-analog Converter Research Articles

A VCO-Based 2nd-Order Δ2–ΔΣ Modulator for Small-Size High Energy-Efficient Current Sensing Front-End

In this letter, a 2nd-order 2 -Σ modulator consisting of a voltage-controlled-oscillator-based quantizer (VCOQ) and a current digital-to-analog converter (DAC) with a pulse width modulator (PWM) is presented for the precise acquisition of a wide range photocurrent in an area-and energy-efficient form factor. The proposed 2-modulation realized by the 2nd-order infinite impulse response (IIR) filter on the feedback significantly attenuates the magnitude of input signals, enhancing the DR and linearity. Moreover, an additional differentiator followed by the VCOQ features the negative feedback loop in the 2nd-order Σ modulator, improving noise shaping with no additional current DAC noise. In addition, a 1-bit PWM current DAC substituting the multi-bit current DAC is devised to mitigate the noise from the current DAC, realizing the high resolution of 1 pA with 500 Hz bandwidth. The prototype chip fabricated in a 110-nm CMOS occupies 0.0308 mm2 and achieves Walden FoM of 4.15 pJ/conv.

Analysis and Design of Low-Complexity Stochastic DEM Encoder for Reduced-Distortion Multi-bit DAC in Sigma-Delta Modulators

A low-complexity stochastic dynamic element matching (DEM) technique to mitigate the distortions caused by the nonlinearity of multi-bit digital-to-analog converters (DACs) in sigma-delta modulator is proposed. Multi-bit DAC noise is analyzed in detail from a signal processing point-of-view in this research, and then implementation of the basic stochastic unit named swapper cell which includes bar state and cross state controlled by a 1-bit pseudo-random noise signal, is illustrated. To reduce the hardware complexity, a multi-layer scheme for multi-input multi-output stochastic encoder is presented and demonstrated based on rigorous mathematical derivation. For a n-input n-output version, the number of the switch elements employed in the proposed encoder is reduced to 2nlog2n from the conventional n!. Simulation results show that, with the use of the stochastic encoder, severe harmonic distortions resulted by the DAC elements mismatch errors are suppressed effectively. When the proposed encoders are applied to the internal multi-bit DACs in sigma-delta (ΣΔ) modulators, large improvements of the linearity performance of the modulators are achieved. Additionally, the analyses and explanations for this stochastic scheme provide a theoretical foundation for the future development of noise shaping DEM.

Mismatch errors randomization for multi-bit DAC in sigma-delta modulators based on butterfly-type network

An alternative mismatch errors randomization scheme for multi-bit digital-to-analog converter (DAC) based on butterfly-type network was proposed. Influences of the mismatch errors on multi-bit DAC and the sigma-delta modulator performances were analyzed in detail. The proposed randomization scheme was applied to the internal DACs in a wideband MASH2-2 sigma-delta modulator. Totally 32 butterfly unit blocks for each randomizer were used to consist of the network and controlled by a 32-bit pseudorandom code to implement randomization on the output thermometer code from the 4-bit flash analog-to-digital converter (ADC). The randomizers had been integrated in the modulator chip, and occupied a total area of about 0.0054 mm2. Experimental results showed that, with the randomizer turned on and over a 12 MHz bandwidth, the signal-to-noise-and-distortion-ratio (SNDR) of the modulator was improved from 79.3 dB to 88.1 dB, the effective-number-of-bits (ENOB) from 12.87-bit to 14.33-bit, and the spurious-free-dynamic-range (SFDR) from 81 dB to 96 dB. The figure of merit (FOM) of the modulator was 40.6-fJ/conv. associated with the improved SNDR.

A 76.6-dB-SNDR 50-MHz-BW 29.2-mW Multi-Bit CT Sturdy MASH With DAC Non-Linearity Tolerance

This article presents a dual-loop noise-coupling (NC)-assisted continuous-time (CT) sturdy multistage noise-shaping (SMASH) $\Delta \Sigma $ modulator (DSM), employing 1.5-bit/4-bit quantizers. The proposed SMASH can equivalently work as an overall fourth-order DSM with 4-bit internal quantization. The NC applied in this CT SMASH DSM whitens the 1.5-bit quantization noise (QN) and further reduces its in-band tone power, while a finite-impulse response (FIR) filter integrated into the outermost feedback path suppresses the out-of-band (OOB) noise power of the multibit digital-to-analog converter (DAC) input. Together, they avoid any linearization technique for the multibit DAC. Sampled at 1.2 GHz, the 28-nm CMOS experimental prototype measures a signal-to-noise-and-distortion ratio (SNDR) of 76.6 dB and a spurious-free dynamic range (SFDR) of 87.9 dB over a 50-MHz bandwidth (BW), consuming 29.2 mW from 1.2-V/1.5-V supplies and occupying an active area of 0.085 mm2. It exhibits a Schreier figure-of-merit (FoM) (SNDR) of 168.9 dB.

A 20-MHz BW MASH Sigma–Delta Modulator with Mismatch Noise Randomization for Multi-Bit DACs

A high-linearity Multi-stAge noise SHaping (MASH) 2–2–2 sigma–delta modulator (SDM) for 20-MHz signal bandwidth (BW) was presented. Multi-bit quantizers were employed in each stage to provide a sufficiently low quantization noise level and thus improve the signal-to-noise ratio (SNR) performance of the modulator. Mismatch noise in the internal multi-bit digital-to-analog converters (DACs) was analyzed in detail, and an alternative randomization scheme based on multi-layer butterfly-type network was proposed to suppress spurious tones in the output spectrum. Fabricated in a 0.18-[Formula: see text]m single–poly 4-metal Complementary Metal Oxide Semiconductor (CMOS) process, the modulator occupied a chip area of 0.45[Formula: see text]mm2, and dissipated a power of 28.8[Formula: see text]mW from a 1.8-V power supply at a sampling rate of 320[Formula: see text]MHz. The measured spurious-free dynamic range (SFDR) was 94[Formula: see text]dB where 17-dB improvement was achieved by applying the randomizers for multi-bit DACs in the first two stages. The peak signal-to-noise and distortion ratio (SNDR) was 76.9[Formula: see text]dB at [Formula: see text]1 dBFS @ 2.5-MHz input, and the figure-of-merit (FOM) was 126[Formula: see text]pJ/conv.

A Dynamic Power Reduction Technique for Incremental $\Delta\Sigma$ Modulators

This paper presents a dynamic power reduction technique for incremental $\Delta \Sigma $ (I- $\Delta \Sigma $ ) modulators. The technique makes use of the unequal weighting of the digital reconstruction filter. The underlying idea is that the input signal samples are not equally weighted in the higher order reconstruction filter. Thus, it is possible to increase the non-idealities of the I- $\Delta \Sigma $ modulator during the runtime of a single Nyquist conversion, thereby saving power. This principal idea is verified by an example design, where the input-referred noise of the first integrator is dynamically increased, which allows for improved efficiency. The proposed technique is readily applicable to every state-of-the-art I- $\Delta \Sigma $ modulator. Furthermore, it is shown that this property can also be used to switch a single-bit digital-to-analog converter (DAC) into a multibit DAC during runtime, thereby greatly improving the achievable signal-to-quantization-noise ratio (SQNR) without suffering from the DAC non-linearity. The prototype I- $\Delta \Sigma $ modulator is manufactured in a 180-nm CMOS technology and achieves a dynamic range/SNDR = 91.5/86.6 dB for a sampling rate of 200 kS/s while consuming l.l mW from a 3-V supply, while the dynamic power reduction method accounts for 30% power savings.

Linear Precoding With Low-Resolution DACs for Massive MU-MIMO-OFDM Downlink

We consider the downlink of a massive multiuser (MU) multiple-input multiple-output (MIMO) system in which the base station (BS) is equipped with low-resolution digital-to-analog converters (DACs). In contrast to most existing results, we assume that the system operates over a frequency-selective wideband channel and uses orthogonal frequency division multiplexing (OFDM) to simplify equalization at the user equipments (UEs). Furthermore, we consider the practically relevant case of oversampling DACs. We theoretically analyze the uncoded bit error rate (BER) performance with linear precoders (e.g., zero forcing) and quadrature phase-shift keying using Bussgang's theorem. We also develop a lower bound on the information-theoretic sum-rate throughput achievable with Gaussian inputs, which can be evaluated in closed form for the case of 1-bit DACs. For the case of multi-bit DACs, we derive approximate, yet accurate, expressions for the distortion caused by low-precision DACs, which can be used to establish the lower bounds on the corresponding sum-rate throughput. Our results demonstrate that, for a massive MU-MIMO-OFDM system with a 128-antenna BS serving 16 UEs, only 3-4 DAC bits are required to achieve an uncoded BER of 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-4</sup> with a negligible performance loss compared to the infinite-resolution case at the cost of additional out-of-band emissions. Furthermore, our results highlight the importance of considering the inherent spatial and temporal correlations caused by low-precision DACs.

An Automatic On-Chip Calibration Technique for Static and Dynamic DAC Error Correction in High-Speed Continuous-Time Delta-Sigma Modulators

Calibration is preferred over dynamic element matching (DEM) techniques to correct nonlinearity in digital-to-analog converters (DACs) in high-speed multi-bit continuous-time (CT) delta-sigma modulators (DSMs) to avoid introducing extra excess loop delay. The state-of-the-art calibration techniques, however, involve substantial external control, making it difficult for a complete on-chip realization. In this paper a highly automated on-chip technique for calibrating differential nonlinearity (DNL) and inter-symbolinterference (ISI) errors of a multi-bit DAC in a CTDSM is presented. The proposed technique implements a Calibration Control System (CCS), equipped with a Finite State Machine (FSM) logic, that automates the entire calibration process with minimal intervention. The calibration loop utilizes the modulator itself to produce the digital estimates of the DNL and the average ISI errors of each unit element of the DAC. These digital estimates are then used to configure auxiliary DACs for correction of the errors in the main DAC. For every unit element in the main DAC, an 8-bit dynamic auxiliary DAC injects a calibrated compensation current in the loop at every up-transition of the input data to cancel the average ISI error, and a 5-bit constant current source array corrects its DNL error. Design considerations and post-layout simulation results for a 50-MHz bandwidth, 1.8GS/s 4 th -order CTDSM are presented. The modulator has a 4.8 dB and a 10.8 dB improvement in SNDR and SFDR respectively with calibration, leading to a dynamic range of 71 dB with a total power consumption of 37.7 mW from 1.3 V and 1 V supplies.

Adaptive Cancellation of Static and Dynamic Mismatch Error in Continuous-Time DACs

Inadvertent but inevitable mismatches among nominally identical unit element 1-bit digital-to-analog converters (DACs) within a multi-bit Nyquist-rate DAC cause both static and dynamic error in the DAC’s continuous-time output waveform. Prior calibration techniques are able to suppress static mismatch error, but have had limited success in suppressing dynamic mismatch error. This paper presents a digital calibration technique that adaptively measures and cancels both static and dynamic mismatch error over the DAC’s first Nyquist band. The technique is capable of either foreground or background operation, and is relatively insensitive to non-ideal circuit behavior. The paper presents a rigorous mathematical analysis of the technique, and demonstrates the results of the paper with both behavioral and transistor-level circuit simulations.

A 6-mW, 70.1-dB SNDR, and 20-MHz BW Continuous-Time Sigma-Delta Modulator Using Low-Noise High-Linearity Feedback DAC

A 4-bit, third-order, continuous-time $\Sigma \Delta$ modulator is presented for use in wireless communications systems. Based on small-signal noise models, analyses for reducing noise in the feedback digital-to-analog converter (DAC) are presented in detail. This enables easy performance/area optimization for the DAC unit elements and the RC noise filter in the DAC bias circuits. To obtain high linearity while simplifying the DAC design, circuit- and layout-level design techniques for minimizing switching time mismatches among and inside the DAC unit elements are presented. As a result, glitch-induced harmonic distortion is greatly reduced, requiring only a simple data-weighted averaging for the multibit DAC. In combination with multipath multistage op amps used to implement active-RC integrators, the presented techniques make it feasible to design a high-performance $\Sigma \Delta$ modulator with low power and small area, which is desired in many wireless communications systems. The experimental prototype, implemented in a 28-nm CMOS technology, achieves a 72.6-dB dynamic range, a 70.7-dB peak SNR, and a 70.1-dB peak signal-to-noise plus distortion ratio for a signal bandwidth of 20 MHz. The total power consumption is 6 mW from a 1- and 1.4-V supply, of which analog and digital circuits dissipate 4.5 and 1.5 mW, respectively. The total active area is 0.058 mm2.

A continuous-time delta-sigma ADC with integrated digital background calibration

This work presents a digital calibration technique in continuous-time (CT) delta-sigma ($$\Delta \Sigma$$ΔΣ) analog to digital converter. The converter is clocked at 144 MHz with a low oversampling ratio (OSR) of only 8. Dynamic element matching is not efficient to linearize the digital to analog converter (DAC) when the OSR is very low. Therefore, non-idealities in the outermost multi-bit feedback DAC are measured and then removed in the background by a digital circuit. A third-order, four-bit feedback, single-loop CT $$\Delta \Sigma$$ΔΣ converter with digital background calibration circuit has been designed, simulated and implemented in 65 nm CMOS process. The maximum simulated signal-to-noise and distortion ratio is 67.1 dB within 9 MHz bandwidth.

A 25 MHz Bandwidth 5th-Order Continuous-Time Low-Pass Sigma-Delta Modulator With 67.7 dB SNDR Using Time-Domain Quantization and Feedback

This paper introduces a continuous-time low-pass sigma-delta modulator operating with a seven-phase 400 <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$\,$</tex> </formula> MHz clocking scheme to control time-based processing in the 3-bit two-step quantizer and main digital-to-analog converter (DAC). An on-chip voltage-controlled oscillator and a complementary injection-locked frequency divider are utilized for low-jitter clock signal generation with multiple phases, allowing 3-bit pulse-width modulated feedback with a single-element DAC to avoid performance degradation from unit element mismatch problems associated with conventional multi-bit DACs.

Analysis of Clock-Jitter Effects in Continuous-Time $\Delta \Sigma $ Modulators Using Discrete-Time Models

This paper proposes a simple discrete-time (DT) modeling technique for the rapid, yet accurate, simulation of the effect of clock jitter on the performance of continuous-time (CT) DeltaSigma modulators. The proposed DT modeling technique is derived from the impulse-invariant transform and is applicable to arbitrary-order lowpass and bandpass CT DeltaSigma modulators, with single-bit or multibit feedback digital-to-analog converters (DACs) employing delayed return-to-zero (RZ) or non-return-to-zero (NRZ) rectangular pulses. Its accuracy is independent of both the power spectrum of the clock jitter and the loop transfer function of the DeltaSigma modulator. The proposed DT modeling technique is validated (for both independent and accumulated clock-jitter errors) against accurate simulations in SIMULINK, using behavioral blocks developed to directly simulate RZ or NRZ DACs with clock jitter. It is subsequently applied to various CT DeltaSigma modulator architectures (low- pass and bandpass, with single-bit and multibit DACs) to study the relative effectiveness of different feedback-DAC pulsing schemes (NRZ, RZ, RZ with fixed on-time, and RZ with fixed off-time) in minimizing the modulator sensitivity to clock jitter. The performance of each architecture is compared as a function of clock jitter, thereby offering a valuable reference for selecting a rectangular feedback-DAC pulse shape when designing CT DeltaSigma analog-to-digital converters.

New Continuous-Time Multibit Sigma–Delta Modulators With Low Sensitivity to Clock Jitter

In this paper, new continuous-time sigma-delta modulators (SDMs) are proposed where the output of a multibit (MB) quantizer is digitally converted to a single-bit pulsewidth-modulated (PWM) signal at a higher rate. The PWM signal is then fed back to the input through a finite-impulse-response digital-to-analog converter (DAC). The proposed modulators are shown to be less sensitive to clock jitter than their equivalent MB SDM, while their amplifiers have similar speed and power requirements. Furthermore, the proposed modulators do not require dynamic-element-matching techniques in the feedback path because a mismatch of the unit elements in the MB DAC does not produce distortion nor increases the noise floor in the signal band.

Measurement and Reduction of ISI in High-Dynamic-Range 1-bit Signal Generation

This paper studies spurious signals produced by the nonlinear interaction of the previous output symbols of a digital-to-analog converter (DAC) with its current symbol. This effect, called nonlinear intersymbol interference (ISI), significantly degrades the spurious-free dynamic range of most high-speed DACs. Many papers have been devoted to suppressing level inaccuracies in multibit DACs. However, even when all levels are accurate, nonlinear ISI causes significant spurious output. This paper presents a simple and very general model for nonlinear ISI and uses it to design binary signals that can both measure and suppress the spurious tones that arise in a single-bit DAC. While the analysis in this paper is based on a 1-bit DAC, extension to multibit DACs is possible, since a multibit DAC is merely a collection of 1-bit DACs and exhibits the same nonlinear effects. Experimental verification is presented for three different hardware setups. Measurements first establish the presence of the spurious tones in the hardware, as predicted by the model, and then show how the spur level can be reduced by as much as 22 dB.

A 100-dB gain-corrected delta-sigma audio DAC with headphone driver

An oversampled digital-to-analog converter (DAC) with a 100-dB A-weighted dynamic range is presented. It uses a switched-capacitor (SC) array to transfer the sampled charges directly into the headphone driver. The overall DAC gain is precisely controlled by a novel reference stage. A new dynamic element matching algorithm, based on split-set data-weighted averaging (SDWA), is used to improve the dynamic range and to reduce the nonlinearity caused by mismatches in the multibit DAC.

Quadrature Mismatch Shaping for Digital-to-Analog Converters

Quadrature sigma-delta analog-to-digital converters require a feedback path for both the I and the Q parts of the complex feedback signal. If two separate multibit feedback digital-to-analog converters (DACs) are used, mismatch among the unit DAC elements leads to additional mismatch noise in the output spectrum as well as an I/Q imbalance. This paper proposes new quadrature bandpass (QBP) mismatch shaping techniques. In our approach, the I and Q DACs are merged into one complex DAC, which leads to near-perfect I/Q balance. To select the unit DAC elements of the complex multibit DAC, the well-known butterfly shuffler and tree structure are generalized towards a complex structure, and necessary constraints for their correct functioning are derived. Next, a very efficient first-order QBP shaper implementation is proposed. Finally, the newly presented complex structures are simulated to prove their effectiveness and are compared with each other with respect to performance

Nonlinearity correction for multibit /spl Delta//spl Sigma/ DACs

This paper presents a digital correction technique for wide-band multibit error-feedback (EF) digital-to-analog converters (DACs). The integral nonlinearity (INL) error of the multibit DAC is estimated (on line or off line) by a calibration analog-to-digital converter (CADC) and stored in a random-access memory table. The INL values are then used to compensate for the multibit DAC's distortion by a simple digital addition. The accuracy requirements for the error estimates are derived. These requirements can be significantly relaxed when the correction is combined with data-weighted averaging (DWA). Simulation and discrete-component measurement results are presented for a fourth-order 5-bit EF DAC. The results show a 14-bit DAC operating at an oversampling ratio of 8, which is suitable for digital subscriber line applications. The correction uses simple digital circuitry and a 3-bit CADC enhanced by DWA.

A Tight Signal-Band Power Bound on Mismatch Noise in a Mismatch-Shaping Digital-to-Analog Converter

Many applications employ digital-to-analog converters (DACs) to obtain the advantages of digital processing (e.g., low power and physical size, resilience to noise, etc.) to generate signals, such as voltages, that are analog in nature. Given the appropriate numerical representation of its input, the DAC ideally behaves as a linear gain element. However, as a result of inevitable component mismatches, the output of a multibit DAC (i.e., a DAC designed to output more than two analog levels) is a nonlinear function of its input. The resulting distortion, called DAC noise , limits the overall signal-to-noise ratio (SNR) and hence the obtainable accuracy of the DAC. Mismatch-shaping DACs exploit built-in redundancy to suppress the DAC noise in the input signal's frequency band. Although mismatch-shaping DACs are widely used in commercial products, little theory regarding the structure of their DAC noise has been published to date. Consequently, designers have been forced to rely upon simulations to estimate DAC noise power and behavior, which can be misleading because the DAC noise depends on the DAC input. This paper addresses this problem. It presents an analysis of the DAC noise power spectral density (PSD) in a commonly used mismatch-shaping DAC: the dithered first-order low-pass tree-structured DAC. This design ensures that its DAC noise has a spectral null at dc (i.e., zero frequency) by generating digital, dc-free sequences using the same techniques that have been developed for line codes. An expression is derived for the DAC noise PSD that depends on the statistics of these sequences and is used to show various properties of the DAC noise. Specifically, an attainable bound is derived for the signal-band DAC noise power that can be used to predict worst case performance in practical circuits.

Digital Noise-Shaping of Residues in Dual-Quantization Sigma–Delta Modulators

A new dual-quantization Sigma-Delta modulator is proposed in this paper where the coarse-quantizer output, obtained from the fine-quantizer output by means of a digital noise-shaping coder, is fed back to the input of the first integrator by means of a p-bit digital-to-analog converter (DAC) (typically, p=1). To avoid the truncation error inserted into the first integrator to propagate to the rest of integrators, the residue of the digital coder is first integrated and then fed to the second integrator through an additional multibit DAC. Unlike other dual-quantization architectures, the proposed one allows to obtain a large signal-to-noise plus distortion ratio by using aggressive noise transfer functions, like in conventional multibit modulators. Mismatch effects on performances are carefully analyzed. It will be shown that more than one digital coder can be included in the architecture in order to reduce the number of bits of the additional DAC. Simulation results are presented which support the theoretical analysis.