Multi-bit Decision Research Articles

Generalized Constituent Nodes for Simplified Successive-Cancellation Decoding of Multi-Kernel Polar Codes

The decoding latency of the successive-cancellation decoder for polar codes is of great importance in its practical applications, and it can be reduced by implementing multi-bit decision decoders in the constituent nodes of the decoding tree. In this letter, we develop a matrix analysis method to analyze the corresponding parity submatrix of the decoding tree’s internal node. Two generalized constituent nodes are presented for the fast simplified successive-cancellation (fast-SSC) decoding of linear kernels-mixed multi-kernel polar codes. Results show that the proposed method achieves latency reduction and preserves the error-correction performance.

In Situ Multi-Bit Decision for Successive Cancellation List Decoding of Polar Codes

In Situ Multi-Bit Decision for Successive Cancellation List Decoding of Polar Codes

Fast Multibit Decision Polar Decoder for Successive-Cancellation List Decoding

Successive-cancellation list (SCL) decoding for polar codes has the disadvantage of high latency owing to serial operations. To improve the latency, several algorithms with additional circuits have been proposed, but the area becomes larger. This paper proposes a fast multibit decision method having-high area efficiency based on the SCL decoding algorithm. First, multiple bits can be determined to reduce clock cycles using new nodes represented by the information bits and frozen bits. We propose the new nodes called the combined nodes and the other node in this paper. The combined nodes that combine redundant operations of the fast-simplified SC (fast-SSC) algorithm can increase area efficiency. The other node with bit patterns other than the node types of the fast-SSC algorithm performs an 8-bit multibit decision to reduce the number of decoding cycles. Latency is further reduced by applying a sphere decoding method to the other node. In addition, a sorter is proposed to reduce the critical path delay. As a large number of path metrics causes sorter delays, the proposed sorter can achieve high throughput with the small area. The proposed (1024, 512) SCL decoder showed negligible performance degradation in the simulation using Matlab and was synthesized using 65 nm CMOS technology. The proposed decoder achieves about 1.3Gbps with the small area. As a result, the area-throughput efficiency is at least 1.4 times higher than the state-of-the-art works over 1 Gbps.

Modeling Design and Implementation of an Embeds System Real Time Over a Network of Wireless Sensors to Environmental Monitoring

Artificial Neurons Network (ANN) is used in the decision and control of dynamic systems which can be with a lack of superfluous information.it forces the use of fuzzy logic.
 
 For this reason, several methods and monitoring techniques have been implemented. This article presents a technique based on artificial neural networks implanted at the level of a multisensor surveillance system. It is a statistical learning method that displays optimal training and generalization performance in several domains, including the recognition domain of forms.
 
 In this case ANN based on raspberry PI card for decision node and arduino for the input and hidden nodes, in order to develop a complete platform environmental monitoring system. and hence enhance multi-Sensor wireless signals aggregation via multi-bit decision fusion. 
 
 The back-propagation algorithm generates a weight for all nodes in the networks, with aim of minimizing absolute error committed in fusion data and economics of electrical energy using artificial intelligence techniques. This algorithm is more efficient than the human being since it can reason and learn from its errors so as not to repeat them.
 
 Its main applications include a variety of data monitoring parameters (such as : temperature, humidity, gas sensor, … etc), that can be found in factory automation, for instance : home automation, remote monitoring and home device control, or it may be used in environment to make an exact decision in short time.

A Flip-Syndrome-List Polar Decoder Architecture for Ultra-Low-Latency Communications

We consider practical hardware implementation of polar decoders. To reduce latency due to the serial nature of successive cancellation, existing optimizations improve parallelism with two approaches, i.e., multi-bit decision or reduced path splitting. In this paper, we combine the two procedures into one with an error-pattern-based architecture. It simultaneously generates a set of candidate paths for multiple bits with pre-stored patterns. For rate-1 (R1) or single parity-check nodes, we prove that a small number of deterministic patterns are required to guarantee performance preservation. For general nodes, low-weight error patterns are indexed by syndrome in a look-up table and retrieved in $O(1)$ time. The proposed flip-syndrome-list decoder fully parallelizes all constituent code blocks without sacrificing performance, and thus is suitable for ultra-low-latency applications. Meanwhile, two code construction optimizations are presented to further reduce complexity and improve performance.

A complexity-reduced fast successive cancellation list decoder for polar codes

A multi-bit decision for polar codes based on a simplified successive cancellation (SSC) decoding algorithm can improve the throughput of polar decoding. A list algorithm is used to improve the error-correcting performance. However, list decoders are highly complex compared with decoders without a list algorithm. In this paper, a low-complexity list decoder is proposed, where path-splitting operations for a multi-bit decision can be avoided, if the decoding reliability exceeds a threshold. The threshold is determined based on the reliability of subchannels and positions of decoding nodes. Path splitting rules are designed for multi-bit decision processes, and a complexity-reduced list decoder is proposed based on this. Results show that the number of survival paths can be greatly reduced at the cost of negligible deterioration in block error performance. Thus, the computational complexity can be significantly reduced, especially for a high signal-to-noise ratio (SNR) region.

LLR-Based Successive-Cancellation List Decoder for Polar Codes With Multibit Decision

Due to their capacity-achieving property, polar codes have become one of the most attractive channel codes. To date, the successive cancellation list (SCL) decoding algorithm is the primary approach that can guarantee outstanding error-correcting performance of polar codes. However, the hardware designs of the original SCL decoder have large silicon area and long decoding latency. Although some recent efforts can reduce either the area or latency of SCL decoders, these two metrics still cannot be optimized at the same time. This paper, for the first time, proposes a general log-likelihood-ratio (LLR)-based SCL decoding algorithm with multi-bit decision. This new algorithm, referred as LLR-2Kb-SCL, can determine 2K bits simultaneously for arbitrary K with the use of LLR messages. In addition, a reduced-data-width scheme is presented to reduce the critical path of the sorting block. Then, based on the proposed algorithm, a VLSI architecture of the new SCL decoder is developed. Synthesis results show that for an example (1024, 512) polar code with list size 4, the proposed LLR-2Kb-SCL decoders achieve significant reduction in both area and latency as compared to prior works. As a result, the hardware efficiency of the proposed designs with K=2 and 3 are 2.33 times and 3.32 times of that of the state-of-the-art works, respectively.

Low-Latency Successive-Cancellation List Decoders for Polar Codes With Multibit Decision

Polar codes, as the first provable capacity-achieving error-correcting codes, have received much attention in recent years. However, the decoding performance of polar codes with traditional successive-cancellation (SC) algorithm cannot match that of the low-density parity-check (LDPC) or turbo codes. Because SC list (SCL) decoding algorithm can significantly improve the error-correcting performance of polar codes, design of SCL decoders is important for polar codes to be deployed in practical applications. However, because the prior latency reduction approaches for SC decoders are not applicable for SCL decoders, these list decoders suffer from the long latency bottleneck. In this paper, we propose a multi-bit-decision approach that can significantly reduce latency of SCL decoders. First, we present a reformulated SCL algorithm that can perform intermediate decoding of 2 bits together. The proposed approach, referred as 2-bit reformulated SCL (2b-rSCL) algorithm, can reduce the latency of SCL decoder from (3n-2) to (2n-2) clock cycles without any performance loss. Then, we extend the idea of 2-bit-decision to general case, and propose a general decoding scheme that can perform intermediate decoding of any 2K bits simultaneously. This general approach, referred as 2K-bit reformulated SCL (2Kb-rSCL) algorithm, can reduce the overall decoding latency to as short as n/2K-2-2 cycles. Furthermore, based on the proposed algorithms, VLSI architectures for 2b-rSCL and 4b-rSCL decoders are synthesized. Compared with a prior SCL decoder, the proposed (1024, 512) 2b-rSCL and 4b-rSCL decoders can achieve 21% and 60% reduction in latency, 1.66 times and 2.77 times increase in coded throughput with list size 2, and 2.11 times and 3.23 times increase in coded throughput with list size 4, respectively.

A Novel Cluster-Based Cooperative Spectrum Sensing with Double Adaptive Energy Thresholds and Multi-Bit Local Decision in Cognitive Radio

The cognitive radio (CR) technique is a useful tool for improving spectrum utilization by detecting and using the vacant spectrum bands in which cooperative spectrum sensing is a key element, while avoiding interfering with the primary user. In this paper, we propose a novel cluster-based cooperative spectrum sensing scheme in cognitive radio with two solutions for the purpose of improving in sensing performance. First, for the cluster header, we use the double adaptive energy thresholds and a multi-bit quantization with different quantization interval for improving the cluster performance. Second, in the common receiver, the weighed HALF-voting rule will be applied to achieve a better combination of all cluster decisions into a global decision.

An Efficient Multibit Aggregation Scheme for Multihop Wireless Sensor Networks

A single-hop wireless sensor network for distributed detection has been considered in the majority of the existing literature. However, a wireless sensor network for an event detection application with cheap and short range sensors is likely to be a multihop network. Here we consider a distributed detection problem in a multihop wireless sensor network with tree topology. We propose an optimum multibit decision fusion rule derived from the previously known optimum likelihood ratio for a single-hop network with star topology. Subsequently, we present an efficient multibit decision fusion rule for a multihop wireless sensor network with tree topology. Through numerical results, the proposed scheme is shown to achieve a significant improvement in detection accuracy over existing distributed detection schemes.