A Flip-Syndrome-List Polar Decoder Architecture for Ultra-Low-Latency Communications

Abstract

We consider practical hardware implementation of polar decoders. To reduce latency due to the serial nature of successive cancellation, existing optimizations improve parallelism with two approaches, i.e., multi-bit decision or reduced path splitting. In this paper, we combine the two procedures into one with an error-pattern-based architecture. It simultaneously generates a set of candidate paths for multiple bits with pre-stored patterns. For rate-1 (R1) or single parity-check nodes, we prove that a small number of deterministic patterns are required to guarantee performance preservation. For general nodes, low-weight error patterns are indexed by syndrome in a look-up table and retrieved in $O(1)$ time. The proposed flip-syndrome-list decoder fully parallelizes all constituent code blocks without sacrificing performance, and thus is suitable for ultra-low-latency applications. Meanwhile, two code construction optimizations are presented to further reduce complexity and improve performance.