Multi-bit Continuous-time Delta-sigma Research Articles

A −89-dBc IMD3 DAC Sub-System in a 465-MHz BW CT Delta-Sigma ADC Using a Power and Area Efficient Calibration Technique

This brief presents a power and area efficient way to measure the feedback DAC static mismatch error in a multi-bit continuous-time delta-sigma modulator. By sequentially forcing each DAC element output in the designed scheme, the mismatch errors among DAC elements can be measured digitally using the ADC itself. The measured errors are then corrected using a two-parameter calibration DAC that tracks temperature variations. An ADC test chip is fabricated in 28-nm CMOS process and it demonstrates IMD3 <−89 dBc with two −9-dBFS tones at 180/190 MHz at room temperature, and 8 dB variation across −10 °C to 120 °C.

A TDC-Based Two-Step Quantizer With Swapper Technique for a Multibit Continuous-Time Delta–Sigma Modulator

A time-to-digital converter (TDC)-based two-step quantizer is proposed for a multibit continuous-time delta–sigma modulator (CTDSM). In the proposed time-domain quantizer, the barrel-shifting operation realizes the dynamic element matching (DEM) function inherently, eliminating an explicit DEM circuit and the associated circuit latency. The two-step quantization scheme further reduces the hardware and power consumption of a multibit TDC quantizer. A swapper technique, in addition to the inherent DEM, is incorporated to randomize the selection of the two banks of digital-to-analog converter cells, which ensure good linearity. A third-order CTDSM incorporating the proposed TDC-based two-step quantizer is fabricated in a 90-nm CMOS process. The modulator achieves a signal-to-noise-and-distortion ratio of 69.6 dB over a 1-MHz signal bandwidth. Operated from 1.2-V analog and 1-V digital supplies, the whole CTDSM consumes 1.79 mW and achieves a figure of merit of 361 fJ/conversion.

A $\Sigma \Delta$-FIR-DAC for Multi-Bit $\Sigma \Delta$ Modulators

In this paper, a new digital-to-analog converter (DAC) is proposed for multi-bit continuous-time sigma-delta modulators (ΣΔMs). This -finite-impulse-response-DAC (ΣΔ-FIR-DAC) digitally converts the multi-bit output of the quantizer to a 1.5-bit signal at a higher rate and then injects it to the modulator loop filter by using a 1.5-bit DAC. An FIR filter is merged into 1.5-bit DAC to improve the clock jitter insensitivity. Furthermore, a new implementation of ΣΔ-FIR-DAC is presented to reduce the output rate of ΣΔ-FIR-DAC down to the original rate of the modulator. This reduced rate ΣΔ-FIR-DAC (RR-ΣΔ-FIR-DAC) can be used in both continuous-time and discrete-time ΣΔMs. Theoretical analysis supported by simulation results are provided to evaluate the performance, clock jitter immunity and robustness against DAC elements mismatch in the proposed modulators.

Systematic Design Methodology of a Wideband Multibit Continuous-Time Delta-Sigma Modulator

Systematic design of a low power, wideband and multi-bit continuous-time delta-sigma modulator (CTDSM) is presented. The design methodology is illustrated with a 640 MS/s, 20 MHz signal bandwidth 4th order 2-bit CTDMS implemented in 0.18 µm CMOS technology. The implemented design achieves a peak SNDR of 65.7 dB and a high dynamic range of 70 dB while consuming only 19.7 mW from 1.8 V supply. The design achieves a FoM of 0.31 pJ/conv. Direct path compensation is employed for one clock excess loop delay compensation. In the feedforward topology, capacitive summation using the last opamp eliminates extra summation opamp.

A 3.1 mW Continuous-Time ΔΣ Modulator With 5-Bit Successive Approximation Quantizer for WCDMA

In this paper, we present a multibit continuous-time delta-sigma modulator based on a 5-bit successive approximation quantizer. The use of successive approximation, instead of flash, is driven by the desire to reduce the quantizer power and area. The quantizer delay is effectively compensated to ensure system stability. The modulator is implemented in a 130 nm CMOS technology and achieves 62 dB of dynamic range over 1.92 MHz while consuming 3.1 mW from a 1.2 V supply.

Continuous time sigma-delta modulator based on binary weighted charge balance

A novel multibit continuous time sigma-delta modulator architecture that does not require a flash converter is presented. The quantiser of this modulator is similar to an integrating ADC that is operated with a binary weighted charge balancing algorithm. The charge residue in the integrating ADC at the end of each conversion cycle is accumulated for the next conversion, providing first-order noise shaping. The modulator order can be increased by the addition of more integrating stages.

Guest editorial: advanced design techniques for wireless communications

This special issue of the Analog Integrated Circuits and Signal Processing presents seven papers in the area of ‘‘Advanced Design Techniques for Wireless Communications’’. New design methodologies, EDA tools and radio transceivers architectures and topologies for emerging wireless technologies are presented. The papers presented in this issue were selected based both on the overall quality of the paper and on the timeliness of the topic. The selected papers reflect continuing trends toward higher levels of analog and digital circuit techniques covering a wide variety of subjects within the Analog Integrated Circuits and Signal Processing fields, ranging from RF/analog and mixed-signal circuits and systems to design methodologies and tools for telecommunications applications. In the first paper, C-Y Wu, W-C Wang, F. R Shahroury, Z-D Huang and H-J Zhan present current-mode design techniques for CMOS RF circuits, which have been developed and employed to implement a 24-GHz CMOS receiver front-end. A receiver front-end, which comprises a current-mode LNA and a current-mode downconversion mixer, has been fabricated in 0.13-lm CMOS technology. The measurement results demonstrate the feasibility of the current-mode techniques for CMOS RF circuits, showing a conversion gain of 11.3 dB, a noise figure of 14.2 dB, the input-referred 1-dB compression point of –13.5 dBm and the input-referred third-order intercept point of -1 dBm. T-Y Lo, C-S Kao and C-C Hung present in their paper a CMOS 3rd order Butterworth low-pass Gm-C filter for multi-mode wireless applications. A transconductor based on flipped-voltage follower circuit and an active resistor working in the strong inversion to achieve the transconductance tuning is designed for multi-mode implementations. The theoretical analysis and a complete set of measurement results demonstrate that the proposed filter is suitable for IEEE 802.11a/b/g/n Wireless LANs. The filter can operate with a cutoff frequency of 10 to 20 MHz, and has a maximum power consumption of 13 mW from a 1.8-V supply voltage. The third paper, by L-F Tanguay and M. Sawan, presents the architectural choices and design of a fully integrated integer-N frequency synthesizer operating in the 902–928 MHz ISM band. This ultra-low power frequency synthesizer is integrated in a transceiver for implantable wireless sensing microsystems, targeting in vivo monitoring of biological parameters. The phase-locked loop-based synthesizer includes a 1.830 GHz LC voltage controlled oscillator using a 10 nH on chip inductor. Varactors are implemented using P? in N-well diodes for their linearity and high quality factor. Several innovative design techniques have been employed to reduce the power consumption of the proposed synthesizer to 580 lW under 1 V, which is almost an order of magnitude lower compared to the recent synthesizer designs having a similar architecture. Yi Ke, S. Radiom, J. Craninkx, G. Vandenbosch and G. Gielen present a systematic design methodology for high-order multi-bit Continuous-Time Sigma-Delta modulators. The proposed strategy provides a straightforward method for determining the coefficients of the modulator, starting with the design of the modulator in z-domain and then converting it into the s-domain. The method is illustrated for a 4th-order 4-bit modulator with an OSR of 8 and a 20 MHz signal bandwidth. The simulation results show A. Rusu (&) M. Ismail ECS, ICT, Royal Institute of Technology (KTH), Stockholm, Sweden e-mail: arusu@kth.se

Analog-to-digital conversion using noise shaping and time encoding

<para xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> Low-voltage CMOS technologies pose new problems in the design of multibit continuous-time sigma-delta modulators. One of these problems is the implementation of the coarse quantizer with an array of voltage comparators. This work presents a novel architecture of multibit continuous-time sigma-delta modulator that employs a time encoding quantizer and irregular sampling instead of a flash analog-to-digital converter. The time-encoding quantizer is based in a modulated oscillator that produces a two-level signal. A digital decoder converts the binary signal into an irregularly sampled multibit signal that is interpolated and fed back into the loop filter of the sigma-delta modulator. This architecture is especially adequate for low-voltage technologies due to the absence of a resistive reference ladder in the quantizer and may permit a significant reduction of the complexity of the existing continuous-time sigma-delta modulators. </para>

Top-down design methodology of a multi-bit continuous-time delta–sigma modulator

Transistor-level simulation of complex systems involving analog and digital parts is a time-consuming task. The growing interaction of analog and digital devices calls for the use of top-down design methodologies, resulting in behavioral modeling at different levels of abstraction. In this article, an advanced design methodology using a combination of behavioral models and transistor-level models is presented. This methodology is very interesting for complex mixed-signal IC design, improving the design flexibility and reducing the simulation time. To validate the proposed methodology, a continuous-time delta---sigma modulator based on a high-speed low-resolution quantizer is modeled, taking into account their nonidealities such as excess loop delay, clock jitter and feedback DAC element mismatch. The main features of the multi-bit quantizer are 3-bit resolution with 4 GHz sampling rate and FOM of about 7 pJ/conv. This modulator samples signals at high-IF, performing directly the analog-to-digital conversion in the modern RF front-end receivers.

A systematic design methodology for power-optimal design of high-order multi-bit continuous-time Delta-Sigma modulators

In this paper a systematic design methodology for high-order multi-bit continuous-time Delta-Sigma modulators is proposed. It provides a straightforward method for determining the coefficients of the modulator. The method is illustrated for a 4th-order 4-bit modulator with OSR of 8, while 20 MHz signal bandwidth and 12 bit resolution is achieved. The required GBW of the first integrator is less than 1.5 times the sampling frequency, which greatly reduces the overall power consumption.

Digital-tuning of RC time constant in Multi-Bit continuous-time Delta-Sigma modulators

In this paper an RC time constant digital-tuning method is proposed for multi-bit continuous-time Delta-Sigma modulators. In this approach the effects of the imprecise RC time constant are compensated in digital domain without any requirement to the conventional analog tuning circuitries. In this method, acquiring the response of the loop-filter of the modulator to a known input signal, the actual loop-gain of the modulator is estimated. Comparing the actual loop-gain and the ideal loop-gain, a proper digital IIR (impulse invariant response) filter is inserted in the feedback path of the modulator. Analytic formulas and MATLAB simulations prove that the proposed method compensates the detrimental effects of the imprecise RC time constant appropriately.

Less jitter sensitive NTF design for NRZ multi-bit continuous-time Delta-Sigma modulators

This paper studies the clock jitter error in multi-bit continuous-time Delta-Sigma modulators with non-return-to-zero (NRZ) feedback waveform. It proposes a few useful formulas for the design of a less jitter sensitive NTF. The analytic results and MATLAB simulations show that in the design of an NTF, there is a trade-off between the in-band quantization noise and the jitter induced noise of the modulator.

Analysis of Integrator Nonlinearity in a Class of Continuous-Time Delta–Sigma Modulators

We analyze the effect of nonlinearity in the first integrator of a single-loop multibit continuous-time delta-sigma modulator, when the loop filter is of the cascade of integrators with feedforward kind. When a multibit quantizer is used in the loop, we show that integrator nonlinearity results in an increased in-band noise (IBN) floor. We develop analytical relations for the IBN spectral density for several opamp topologies, assuming that the shaped quantization noise is approximately Gaussian. Our results agree well with macromodel and transistor level simulations.

Clock jitter error in multi-bit continuous-time sigma-delta modulators with non-return-to-zero feedback waveform

This paper presents a detailed study of the clock jitter error in multi-bit continuous-time ΣΔ modulators with non-return-to-zero feedback waveform. It is demonstrated that jitter-induced noise power can be separated into two main components: one that depends on the modulator loop-filter transfer function and the other dependent on input signal parameters, i.e. amplitude and frequency. The latter component, not considered in previous approaches, allows us accurately to predict the resolution loss caused by jitter, showing effects not taken into account previously in literature despite the fact that they are especially critical in broadband telecom applications. Moreover, the use of state-space formulation makes the analysis quite general and applicable to either cascade or single-loop architectures. Closed-form expressions are derived for in-band error power and signal-to-noise ratio that can be used to optimize modulator performance in terms of jitter insensitivity. Time-domain simulations of several modulator topologies (both single-loop and cascade) intended for VDSL application demonstrate the validity of the presented approach.

A New Infrastructure for Digital Pre-Filtering in Multi-bit Continuous Time Delta Sigma Modulators

In this paper a new approach for employing the digital signal processing capabilities in the design of the multi-bit continuous time (CT) Delta Sigma modulators (DSM's) is presented. It proposes the discrete time (DT) pre-filtering before the DAC for solving the known problems of the CT DSM's.