Systematic Design Methodology of a Wideband Multibit Continuous-Time Delta-Sigma Modulator

Awinash Anand,Haruichi Kanaya,Nischal Koirala,Ramesh K Pokharel,Keiji Yoshida

doi:10.1155/2013/275289

Abstract

Systematic design of a low power, wideband and multi-bit continuous-time delta-sigma modulator (CTDSM) is presented. The design methodology is illustrated with a 640 MS/s, 20 MHz signal bandwidth 4th order 2-bit CTDMS implemented in 0.18 µm CMOS technology. The implemented design achieves a peak SNDR of 65.7 dB and a high dynamic range of 70 dB while consuming only 19.7 mW from 1.8 V supply. The design achieves a FoM of 0.31 pJ/conv. Direct path compensation is employed for one clock excess loop delay compensation. In the feedforward topology, capacitive summation using the last opamp eliminates extra summation opamp.

Highlights

Delta-sigma modulators embed low-resolution analog-todigital converter in a feedback loop
To illustrate the design methodology, a 4th-order 2-bit continuous-time delta-sigma modulator is designed in 0.18 μm CMOS technology
The design consumes overall power of 19.7 mW to achieve a figure of merit (FoM) of 0.31 pJ/conv

Summary

Introduction

Delta-sigma modulators embed low-resolution analog-todigital converter in a feedback loop. Excess loop delay compensation is for more than one clock, where, to achieve higher resolution, higher bit quantizer should be used. These all increase the design methodology complexity and are not simple to adopt for designers. To keep the design simple and the insight intact, we implement one-step quantizer with excess loop delay compensation for one clock. In [4], the optimal design methodology of a higher-order continuoustime wideband delta-sigma modulator is presented. This methodology requires summation amplifier and consumes higher power. In [4] SNR and phase margin are optimized which could be replaced to simpler way to optimize the peak SNR and the maximum stable amplitude which are more obvious parameters

Objectives

Results

Conclusion