Multi-bit Continuous-time Delta-sigma Modulator Research Articles

A −89-dBc IMD3 DAC Sub-System in a 465-MHz BW CT Delta-Sigma ADC Using a Power and Area Efficient Calibration Technique

This brief presents a power and area efficient way to measure the feedback DAC static mismatch error in a multi-bit continuous-time delta-sigma modulator. By sequentially forcing each DAC element output in the designed scheme, the mismatch errors among DAC elements can be measured digitally using the ADC itself. The measured errors are then corrected using a two-parameter calibration DAC that tracks temperature variations. An ADC test chip is fabricated in 28-nm CMOS process and it demonstrates IMD3 <−89 dBc with two −9-dBFS tones at 180/190 MHz at room temperature, and 8 dB variation across −10 °C to 120 °C.

A TDC-Based Two-Step Quantizer With Swapper Technique for a Multibit Continuous-Time Delta–Sigma Modulator

A time-to-digital converter (TDC)-based two-step quantizer is proposed for a multibit continuous-time delta–sigma modulator (CTDSM). In the proposed time-domain quantizer, the barrel-shifting operation realizes the dynamic element matching (DEM) function inherently, eliminating an explicit DEM circuit and the associated circuit latency. The two-step quantization scheme further reduces the hardware and power consumption of a multibit TDC quantizer. A swapper technique, in addition to the inherent DEM, is incorporated to randomize the selection of the two banks of digital-to-analog converter cells, which ensure good linearity. A third-order CTDSM incorporating the proposed TDC-based two-step quantizer is fabricated in a 90-nm CMOS process. The modulator achieves a signal-to-noise-and-distortion ratio of 69.6 dB over a 1-MHz signal bandwidth. Operated from 1.2-V analog and 1-V digital supplies, the whole CTDSM consumes 1.79 mW and achieves a figure of merit of 361 fJ/conversion.

Systematic Design Methodology of a Wideband Multibit Continuous-Time Delta-Sigma Modulator

Systematic design of a low power, wideband and multi-bit continuous-time delta-sigma modulator (CTDSM) is presented. The design methodology is illustrated with a 640 MS/s, 20 MHz signal bandwidth 4th order 2-bit CTDMS implemented in 0.18 µm CMOS technology. The implemented design achieves a peak SNDR of 65.7 dB and a high dynamic range of 70 dB while consuming only 19.7 mW from 1.8 V supply. The design achieves a FoM of 0.31 pJ/conv. Direct path compensation is employed for one clock excess loop delay compensation. In the feedforward topology, capacitive summation using the last opamp eliminates extra summation opamp.

A 3.1 mW Continuous-Time ΔΣ Modulator With 5-Bit Successive Approximation Quantizer for WCDMA

In this paper, we present a multibit continuous-time delta-sigma modulator based on a 5-bit successive approximation quantizer. The use of successive approximation, instead of flash, is driven by the desire to reduce the quantizer power and area. The quantizer delay is effectively compensated to ensure system stability. The modulator is implemented in a 130 nm CMOS technology and achieves 62 dB of dynamic range over 1.92 MHz while consuming 3.1 mW from a 1.2 V supply.

Top-down design methodology of a multi-bit continuous-time delta–sigma modulator

Transistor-level simulation of complex systems involving analog and digital parts is a time-consuming task. The growing interaction of analog and digital devices calls for the use of top-down design methodologies, resulting in behavioral modeling at different levels of abstraction. In this article, an advanced design methodology using a combination of behavioral models and transistor-level models is presented. This methodology is very interesting for complex mixed-signal IC design, improving the design flexibility and reducing the simulation time. To validate the proposed methodology, a continuous-time delta---sigma modulator based on a high-speed low-resolution quantizer is modeled, taking into account their nonidealities such as excess loop delay, clock jitter and feedback DAC element mismatch. The main features of the multi-bit quantizer are 3-bit resolution with 4 GHz sampling rate and FOM of about 7 pJ/conv. This modulator samples signals at high-IF, performing directly the analog-to-digital conversion in the modern RF front-end receivers.

A systematic design methodology for power-optimal design of high-order multi-bit continuous-time Delta-Sigma modulators

In this paper a systematic design methodology for high-order multi-bit continuous-time Delta-Sigma modulators is proposed. It provides a straightforward method for determining the coefficients of the modulator. The method is illustrated for a 4th-order 4-bit modulator with OSR of 8, while 20 MHz signal bandwidth and 12 bit resolution is achieved. The required GBW of the first integrator is less than 1.5 times the sampling frequency, which greatly reduces the overall power consumption.

Digital-tuning of RC time constant in Multi-Bit continuous-time Delta-Sigma modulators

In this paper an RC time constant digital-tuning method is proposed for multi-bit continuous-time Delta-Sigma modulators. In this approach the effects of the imprecise RC time constant are compensated in digital domain without any requirement to the conventional analog tuning circuitries. In this method, acquiring the response of the loop-filter of the modulator to a known input signal, the actual loop-gain of the modulator is estimated. Comparing the actual loop-gain and the ideal loop-gain, a proper digital IIR (impulse invariant response) filter is inserted in the feedback path of the modulator. Analytic formulas and MATLAB simulations prove that the proposed method compensates the detrimental effects of the imprecise RC time constant appropriately.

Less jitter sensitive NTF design for NRZ multi-bit continuous-time Delta-Sigma modulators

This paper studies the clock jitter error in multi-bit continuous-time Delta-Sigma modulators with non-return-to-zero (NRZ) feedback waveform. It proposes a few useful formulas for the design of a less jitter sensitive NTF. The analytic results and MATLAB simulations show that in the design of an NTF, there is a trade-off between the in-band quantization noise and the jitter induced noise of the modulator.

Analysis of Integrator Nonlinearity in a Class of Continuous-Time Delta–Sigma Modulators

We analyze the effect of nonlinearity in the first integrator of a single-loop multibit continuous-time delta-sigma modulator, when the loop filter is of the cascade of integrators with feedforward kind. When a multibit quantizer is used in the loop, we show that integrator nonlinearity results in an increased in-band noise (IBN) floor. We develop analytical relations for the IBN spectral density for several opamp topologies, assuming that the shaped quantization noise is approximately Gaussian. Our results agree well with macromodel and transistor level simulations.