Multi-application Mapping Research Articles

A performance-centric ML-based multi-application mapping technique for regular Network-on-Chip

This research article discusses the challenges faced by the Network-on-Chip (NoC) architecture due to increased integration density and proposes a novel fault-tolerant multi-application mapping approach called ”FANC.” The approach is based on Machine Learning (ML) and can provide solutions for unseen graphs and topologies without prior training. The proposed technique uses an ML-based model to extract relevant information from the search data and incorporate it into the search process. This results in a more robust model with a higher convergence rate and solution quality. The approach is evaluated using a variety of simulation parameters, such as communication cost, network latency, throughput, and power usage. Static simulations are performed in a Python programming environment, while dynamic simulations are performed with a SystemC-based cycle-accurate NoC simulator and the Orion2.0 Power tool. The results show that FANC reduces communication costs by 266%. It also improves network latency by 9%, throughput by 1%, and power consumption by 7%. The approach also simplifies and minimizes the search area in the design exploration process and can be used as an auxiliary component for other optimization algorithms.

A Multi-Phase Based Multi-Application Mapping Approach for Many-Core Networks-on-Chip.

More and more attention is being paid to the use of massive parallel computing performed on many-core Networks-on-Chip (NoC) in order to accelerate performance. Simultaneously deploying multiple applications on NoC is one feasible way to achieve this. In this paper, we propose a multi-phase-based multi-application mapping approach for NoC design. Our approach began with a rectangle analysis, which offered several potential regions for application. Then we mapped all tasks of the application into these potential regions using a genetic algorithm, and identified the one which exhibited the strongest performance. When the packeted regions for each application were identified, a B*Tree-based simulated annealing algorithm was used to generate the optimal placement for the multi-application mapping regions. The experiment results show that the proposed approach can achieve a considerable reduction in network power consumption (up to 23.45%) and latency (up to 24.42%) for a given set of applications.

Multi-Application Mapping onto a Switch-Based Reconfigurable Network-on-Chip Architecture

This paper presents a reconfigurable architecture for Network-on-Chip (NoC) design based on configuration switches. Reconfiguration is achieved by varying connection pattern between routers, depending on the currently running application. Mapping and reconfiguration strategies have been developed for the proposed architecture. In the mapping phase, cores in the combined application set are mapped to individual routers, minimizing the overall communication cost. In the second phase, for each application, configuration information for the switches (between the routers) are generated to optimize the communication cost further to suit the corresponding application. Exact methods, based on Integer Linear Programming (ILP), have been proposed for both the phases. Since ILP takes a large amount of CPU time, Particle Swarm Optimization (PSO)-based approaches have also been developed. The architecture and mapping strategies have been evaluated against benchmarks, considering communication cost, throughput, latency and network energy before and after reconfiguration. Significant improvements could be achieved via reconfiguration. Compared to the approaches reported in the literature, communication cost, throughput, latency and energy consumption values improve by 23.4%, 4%, 3% and 7%, respectively. These improvements come at a nominal increase in area overhead of 0.07%.

Online multi-application mapping in photonic Network-on-Chip with mesh topology

The silicon photonic interconnection is one of the promising solutions with high bandwidth and low power consumption for overcoming electrical Network-on-Chip challenges. This communication infrastructure provides, to integrate hundreds processing cores on a chip, then this structure is suitable for running multi-application simultaneously. In this paper, a chain of algorithms have been proposed for online multi-application mapping in Photonic Network-on-Chip (PNoC). This chain contains Boundary allocation, Boundary migration and inter sub-mesh Loss Aware (LA) mapping for improving performance constrained parameter. Experimental results indicate a considerable improvement of combining the Boundary allocation and migration scheme, about 33.8% improvement in average execution time and 37.6% in energy deception.

Temperature-aware multi-application mapping on network-on-chip based many-core systems

As the number of processor cores increases and the core size shrinks, chip temperature has become a critical design issue for Network-on-Chip (NoC) based many-core systems. However, few task mapping methods consider temperature optimization, and even fewer in multi-application scenarios. In this paper, we propose a temperature-aware multi-application mapping scheme for NoC-based many-core systems. Chip temperature is reduced by balancing workloads among cores while few communication overheads are introduced. The applications are firstly partitioned into subgraphs, and the inter-subgraph communication is minimized. A submesh region is then allocated to each subgraph so as to avoid long distance communication. The processing speed of each core is estimated to decide the submesh size according to current temperature distribution, so the submesh allocation is efficient for balanced core temperatures. Finally, task mapping within each pair of subgraph and submesh is performed. The core temperatures, the heating of adjacent cores, chip layout and communication overheads are all considered. Besides, the voltage and frequency level of each task is also scaled down for temperature reduction while timing constraints are guaranteed. Experimental results show that the peak temperature is reduced by 4.8°C compared to current approaches and the temperature variance is reduced to 42% of the initial temperature variance. The energy consumption and communication overheads are also reduced.