Mu M-gate Research Articles

High-Frequency ZnO Thin-Film Transistors on Si Substrates

Record microwave frequency performance was achieved with nanocrystalline ZnO thin-film transistors fabricated on Si substrates. Devices with 1.2-mum gate lengths and Au-based gate metals had current and power gain cutoff frequencies of f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> = 2.45 GHz and f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">max</sub> = 7.45 GHz, respectively. Same devices had drain-current on/off ratios of 5 times10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">10</sup> exhibited no hysteresis effects and could be operated at a current density of 348 mA/mm. The microwave performances of devices with 1.2- and 2.1- mum gate lengths and 50- and 100-mum gate widths were compared.

AlGaN/GaN MOS-HEMT With $\hbox{HfO}_{2}$ Dielectric and $\hbox{Al}_{2}\hbox{O}_{3}$ Interfacial Passivation Layer Grown by Atomic Layer Deposition

We have developed a novel AlGaN/GaN metal-oxide-semiconductor high-electron mobility transistor using a stack gate HfO2/Al2O3 structure grown by atomic layer deposition. The stack gate consists of a thin HfO2 (30-A) gate dielectric and a thin Al2O3 (20- A) interfacial passivation layer (IPL). For the 50-A stack gate, no measurable C-V hysteresis and a smaller threshold voltage shift were observed, indicating that a high-quality interface can be achieved using a Al2O3 IPL on an AlGaN substrate. Good surface passivation effects of the Al2O3 IPL have also been confirmed by pulsed gate measurements. Devices with 1- mum gate lengths exhibit a cutoff frequency (fT) of 12 GHz and a maximum frequency of oscillation (f MAX) of 34 GHz, as well as a maximum drain current of 800 mA/mm and a peak transconductance of 150 mS/mm, whereas the gate leakage current is at least six orders of magnitude lower than that of the reference high-electron mobility transistors at a positive gate bias.

1 µm gate length, In 0.75 Ga 0.25 As channel, thin body n-MOSFET on InP substrate with transconductance of 737 µS/μm

The first demonstration of implant-free, flatband-mode In 0.75 Ga 0.25 As channel n-MOSFETs is reported. These 1 mum gate length MOSFETs, fabricated on a structure with average mobility of 7720 cm /Vs and sheet carrier concentration of 3.3 times 10 cm -2 , utilise a Pt gate, a high-k dielectric (k sime 20), and a delta-doped InAlAs/InGaAs/InAlAs heterostructure. The devices have a typical maximum drive current (I d,sat ) of 933 muA/mum, extrinsic transconductance (g m ) of 737 muS/mum, gate leakage (I g ) of 40 pA, and on-resistance (R on ) of 555 Omega .mum. The g m and R on figures of merit are the best reported to date for any III-V MOSFET.

Fabrication and Performance of 0.25-$\mu$m Gate Length Depletion-Mode GaAs-Channel MOSFETs With Self-Aligned InAlP Native Oxide Gate Dielectric

The fabrication and performance of 0.25- mum gate length GaAs-channel MOSFETs using the wet thermal native oxide of InAlP as the gate dielectric are reported. A fabrication process that self-aligns the gate oxidation to the gate recess and metallization to reduce the source access resistance is demonstrated for the first time. The fabricated devices exhibit a peak extrinsic transconductance of 144 mS/mm, an on-resistance of 3.46 Omega-mm, and a threshold voltage of -1.8 V for typical 0.25 -mum gate devices. A record cutoff frequency of 31 GHz for a GaAs-channel MOSFET and a maximum frequency of oscillation f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">max</sub> of 47 GHz have also been measured.

A low phase-noise X-band MMIC VCO using high-linearity and low-noise composite-channel Al0.3Ga0.7N/Al0.05Ga0.95N/GaN HEMTs

A low phase-noise X-band monolithic-microwave integrated-circuit voltage-controlled oscillator (VCO) based on a novel high-linearity and low-noise composite-channel Al0.3Ga0.7N/Al0.05Ga0.95 N/GaN high electron mobility transistor (HEMT) is presented. The HEMT has a 1 mumtimes100 mum gate. A planar inter-digitated metal-semiconductor-metal varactor is used to tune the VCO's frequency. The polyimide dielectric layer is inserted between a metal and GaN buffer to improve the Q factor of spiral inductors. The VCO exhibits a frequency tuning range from 9.11 to 9.55 GHz with the varactor's voltage from 4 to 6 V, an average output power of 3.3 dBm, and an average efficiency of 7% at a gate bias of -3 V and a drain bias of 5 V. The measured phase noise is -82 dBc/Hz and -110 dBc/Hz at offsets of 100 kHz and 1 MHz at a varactor's voltage (Vtune)=5 V. The phase noise is the lowest reported thus far in VCOs made of GaN-based HEMTs. In addition, the VCO also exhibits the minimum second harmonic suppression of 47 dBc. The chip size is 1.2times1.05 mm2

Pseudomorphic n-InGaP/InGaAs/GaAs high electron mobility transistors for low-noise amplifiers

The authors developed 0.15- mu m-gate pseudomorphic n-InGaP/InGaAs/GaAs HEMTs for low-noise amplifiers. Passivated devices exhibited a noise figure of 0.41 dB with an associated gain of 13.0 dB at 12 GHz including package loss, and of 1.2 dB with an associated gain of 5.8 dB at 50 GHz. Reducing the short-channel effects was the key to achieving the best performance ever reported for passivated and packaged low-noise HEMTs on GaAs substrates. A high aspect ratio under the thin n-InGaP layer and good carrier confinement in the pseudomorphic InGaAs channel reduce the undesirable short-channel effects in these devices. >

Integration of microsensors in GaAs MESFET process

Piezoelectric pressure sensors and pyroelectric infrared detectors based on ZnO thin films have been integrated with GaAs metal-semiconductor field effect transistor (MESFET) amplifiers. The microsensors incorporate a 1 mu m-thick sputtered ZnO capacitor supported by a 2 mu m-thick aluminium membrane formed on a semi-insulating GaAs substrate. The piezoelectric pressure sensor of area 80*80 mu m2 exhibits 2.99 mu V mu bar-1 sensitivity at 400 Hz. The voltage response of a single infrared detector of area 80*80 mu m2 is 6.2 mV at 10 Hz and the time constant is 53 ms. Circuits using 4 mu m-gate GaAs MESFETs are fabricated using a planar, direct ion-implant process. The measured transconductance of a 4 mu m-gate GaAs MESFET is 25.6 mS. mm-1 at room temperature.

0.1- mu m-gate, ultrathin-film CMOS devices using SIMOX substrate with 80-nm-thick buried oxide layer

A 0.1- mu m-gate CMOS/SIMOX (separation by implanted oxygen) has been successfully fabricated using high quality SIMOX substrates and an advanced design concept for the subquarter-micron region based on a simple device model. In addition, both 85-nm-gate n- and p-MOSFETs/SIMOX with 8-nm-thick silicon active layer have been realized. High parasitic resistance in the source and drain regions of the 0.1- mu m-gate CMOS/SIMOX tends to increase the propagation delay time. However, 0.1- mu m-gate CMOS/SIMOX devices with a delay time as low as 10 ps can be obtained by reducing the parasitic resistance. >

A 20-Gb/s flip-flop circuit using direct-coupled FET logic

A new type of direct-coupled FET logic (DCFL) flip-flop called the memory cell type flip-flop (MCFF) is presented. The MCFF operates faster than conventional DCFL flip-flops and enhances the DCFL's advantages, such as low power consumption and high packing density. A D-flip-flop IC and a 1/8 divider IC were developed using the MCFF. These ICs were fabricated using 0.2- mu m-gate pseudomorphic inverted HEMTs. The D-flip-flop IC is confirmed to operate up to 20 Gb/s. The 1/8 divider is toggled up to a maximum frequency of 25 GHz. These results prove that the MCFF enables DCFL circuits applicable not only to large-scale integration but to small-scale and medium-scale integration operating up to 20 Gb/s as well.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Simulation and fabrication of submicron channel length DMOS transistors for analog applications

The use of an asymmetric MOS structure for superior analog circuit performance is considered. Results from the fabrication of 1- mu m-gate length DMOS transistors show increases of up to 1.9 in transconductance, 10 in output resistance, and 8 in intrinsic gain when compared to NMOS structures of similar gate length and threshold voltage. Substrate current is also reduced by up to a factor of 10. This represents the first reported results of submicron channel length DMOS transistors. The standard 7 degrees implantation angle has significant impact on DMOS fabrication and is shown to produce a usable asymmetric DMOS from an otherwise symmetric DMOS. An optimal implant energy and diffusion time are shown to exist for DMOS enhancement region formation. Two-dimensional process and device simulators have proved necessary to develop the DMOS process, as well as to qualitatively explain body effect reduction and threshold voltage determination. The DMOS process has successfully yielded experimental circuits including a single ended operational amplifier of folded cascode technology and a 101-state ring oscillator. >

Characterization and high-speed digital application of GaAs MESFETs on substrates

Summary form only given. The authors optimized the device structure to suppress the short channel effect due to the residual stress in GaAs/Si substrates and improved the microscopic uniformity. The residual-stress problem was solved by introducing a p-layer (C/sup +/: 140 keV) buried under the n-type channel (Si/sup +/: 20 keV) in the n/sup +/ self-alignment technique with refractory W-Al gate. The authors then evaluated the microscopic uniformity of the device on GaAs/Si using 60- mu m*60- mu m-pitch FET arrays, and found that it is improved by introducing the p-layer. To evaluate the dynamic characteristics, a direct-coupled FET logic (DCFL) ring oscillator was fabricated using a 0.3- mu m-gate MESFET on the GaAs/Si substrate. The propagation delay was as small as 19.9 ps/gate at a supply voltage of 2 V. >

Super-low-noise performance of direct-ion-implanted 0.25- mu m-gate GaAs MESFET's

The authors report on advanced ion implantation GaAs MESFET technology using a 0.25- mu m 'T' gate for super-low-noise microwave and millimeter-wave IC applications. The 0.25*200- mu m-gate GaAs MESFETs achieved 0.56-dB noise figure with 13.1-dB associated gain at 50% I/sub DSS/ and 0.6 dB noise figure with 16.5-dB associated gain at 100% I/sub DSS/ at a measured frequency of 10 GHz. The measured noise figure is comparable to the best noise performance of AlGaAs/GaAs HEMTs and AlGaAs/InGaAs/GaAs pseudomorphic HEMTs.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

A high-speed and highly uniform submicrometer-gate BPLDD GaAs MESFET for GaAs LSIs

The authors present formation conditions for ion-implanted regions of a GaAs buried p-layer lightly doped drain (BPLDD) MESFET that can improve short-channel effect, V/sub th/ uniformity, and FET operating speed, simultaneously. For 0.7- mu m gates, a Mg/sup +/ dose of 2*10/sup 12/ cm/sup -2/ at 300 keV and a Si/sup +/ dose of 2*10/sup 12/ cm/sup -2/ at 50 keV are suitable for the p layer and n' layer, respectively. A sigma V/sub th/ of 7 mV is realized. Gate-edge capacitance of the 0.7- mu m-gate BPLDD that consists of both overlap capacitance and fringing capacitance is successfully reduced to 0.5 fF/ mu m, which is about 50% of that of a non-LDD buried p-layer (BP) FET. Another parasitic capacitance due to the p-layer was found to have less effect on the speed than the gate-edge one. Consequently, the gate propagation delay time of the BPLDD can be reduced to 15 ps at power dissipation of 1 mW/gate, which is about 65% of that of a BP. Applying the 0.7- mu m-gate BPLDD to 16-kb SRAMs, the authors have obtained a maximum access time of less than 5 ns with a galloping test pattern.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Monolithically integrated InP-based front-end photoreceivers

The performance characteristics of a monolithically integrated front-end photoreceiver, consisting of a photodiode and a MODFET amplifier, were analyzed and measured. A vertical scheme of integration was initially used to realize a photoreceiver circuit on InP consisting of an InGaAs p-i-n diode, an InGaAs/InAlAs pseudomorphic MODFET, and passive circuit elements. The device structures were grown by single-step molecular beam epitaxy with an isolating layer in between. The microwave performance of 1- mu m-gate MODFETs in the circuit is characterized by f/sub T/=9 GHz, although identical discrete devices have f/sub T/=30-35 GHz. The degradation is due to additional parasitic capacitances present in this integration scheme. In spite of this disadvantage the bandwidth of the circuit is 2.1 GHz. Integration of the p-i-n diode with 1.0- and 0.25- mu m-gate MODFETs has also been done in a planar scheme using regrowth, and receiver bandwidths of 6.5 GHz were measured. This value is comparable to that of hybrid circuits with InP-based devices.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Effects of neutral buried p-layer on high-frequency performance of GaAs MESFETs

Fully ion-implanted n/sup +/ self-aligned GaAs MESFETs with Au/WSiN refractory metal gates have been fabricated by adopting neutral buried p-layers formed by 50-keV Be-implantation. S-parameter measurements and equivalent circuit fittings are discussed. When the Be dose is increased from 2*10/sup 12/ cm/sup -2/ to 4*10/sup 12/ cm/sup -2/, the maximum value of the cutoff frequency with a 0.2- mu m gate falls off from 108 to 78 GHz. This is because a neutral buried player makes the intrinsic gate-source capacitance increase markedly, while its influence on gate-drain capacitance and gate-source fringing capacitance is negligible. The maximum oscillation frequency recovers, however, due primarily to the drain conductance suppression by the higher-concentration buried p-layer. An equivalent value of over 130 GHz has been obtained for both 0.2- mu m-gate GaAs MESFETs.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

A 45 K-gate HEMT array with 35-ps DCFL and 50-ps BDCFL gates

A 45 K-gate emitter-coupled-logic (ECL)-compatible array with unbuffered and buffered direct-coupled FET-logic (DCFL and BDCFL) gates has been developed using 0.6- mu m-gate high-electron-mobility transistors (HEMTs) and four-level gold-based interconnects. The high-speed DCFL gates and more functional BDCFL gates are used to replace ECL macros efficiently. The basic cell, equivalent to four three-input NOR gates, consists of 12 enhancement-mode (E-mode) HEMTs, four depletion mode (D-mode) HEMTs, and two source-follower buffers. The basic gate delay times are 35 ps for 0.24-mW unbuffered DCFL gates and 50 ps for 0.38-mW BDCFL gates. The gate array chip is 9.8*9.8 mm and contains 45600 gates. The chip dissipates 11 W in 80% gate use. Silylated polymethyl silsequioxane (PMSS), which has a low dielectric constant of 3, is used for the interlayer dielectrics to reduce wiring delay.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

X-band MMIC amplifier with pulse-doped GaAs MESFET's

The design and test of an X-band monolithic four-stage low-noise amplifier (LNA) with 0.5 mu m-gate pulse-doped GaAs MESFETs for application in a direct broadcast satellite (DBS) converter is presented. The key feature of the research is a detailed demonstration of the advantages of using series feedback with experiments and simulations. This LNA shows an excellent input VSWR match under 1.4 as well as a noise figure of 1.67 dB and a gain of 24 dB at 12 GHz. The noise figure, the gain and VSWRs exhibit very little bias current dependence due to the exceptional features of the pulse-doped structure FETs and the optimized circuit design. Insensitivity to bias current implies performance stability in the face of process fluctuations. Thus, the yield of chips with noise figures of less than 2.0 dB is as high as 62.5%, and the variations of gain and VSWR are highly uniform as well. >

Highly lattice-mismatched In/sub 0.26/Ga/sub 0.74/As/GaAs MESFET's: impact of critical thickness on device performance

Fabrication of 0.25- mu m-gate MESFETs directly on In/sub 0.26/Ga/sub 0.74/As epitaxial layers which are much thicker than the pseudomorphic critical thickness is described. The InAs mole fraction is increased in the MESFET channel to 26%. Whether the device performance can be further improved without detrimental dislocation effects as the channel thickness exceeds the critical thickness considerably is investigated. Despite large lattice mismatch and high defect density, these devices show excellent microwave performance with an extrinsic f/sub t/ of 120 GHz. Bias-dependent S-parameters indicate that the In/sub 0.26/Ga/sub 0.74/As MESFET maintains excellent device performance down to very low drain current without showing any performance degradation due to misfit or threading dislocations. >

MOCVD-grown 0.25- mu m MESFET's using tertiary butyl arsine as the arsenic source

High-performance 0.25- mu m-gate MESFETs on MOCVD-grown epitaxial structure have been fabricated using tertiary butyl arsine (TBA) as the arsenic source. TBA, a liquid-phase organometallic arsenic compound, is a promising alternate arsenic source due to its lower vapor pressure, which makes it safer to handle than arsine. DC characterizations show that the extrinsic peak transconductance is 508 mS/mm. From on-wafer S-parameter measurements, the MESFETs show a current-gain cutoff frequency of 55 GHz and a maximum-available-gain cutoff frequency of 93 GHz. These results represent the best results reported for MOCVD-grown MESFETs using a TBA source and compare favorably with the previously reported f/sub t/ of 40 GHz for molecular beam epitaxy (MBE)-grown MESFETs. >

New continuous heterostructure field-effect-transistor model and unified parameter extraction technique

A continuous model for heterostructure field-effect transistors (HFETs) suitable for circuit simulation and device characterization is proposed. The model is based on the analytical solution of a two-dimensional Poisson equation in the saturation region. The HFET saturation current and saturation voltage have been experimentally determined by differentiating the output characteristics in a unified and unambiguous way. The results are used for the systematic extraction of device and process parameters. The deduced values agree well with other independent measurements. The results of experimental studies of HFETs with nominal gate lengths of 1, 1.4, 2, and 5 mu m are reported. The models and techniques presented here are successfully applied to all these devices. A large short-channel effect is observed for the 1- mu m-gate HFET. The gate length dependences of the device parameters determined by the method reveal that the effective gate length in the self-aligned structures is approximately 0.25 mu m shorter than the nominal gate length.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>