MPSoC Platform Research Articles

Automatic Synthesis of FSMs for Enforcing Non-functional Requirements on MPSoCs Using Multi-objective Evolutionary Algorithms

Embedded system applications often require guarantees regarding non-functional properties when executed on a given MPSoC platform. Examples of such requirements include real-time, energy, or safety properties on corresponding programs. One option to implement the enforcement of such requirements is by a reactive control loop, where an enforcer decides based on a system response (feedback) how to control the system, e.g., by adapting the number of cores allocated to a program or by scaling the voltage/frequency mode of involved processors. Typically, a violation of a requirement must either never happen in case of strict enforcement, or only happen temporally (in case of so-called loose enforcement). However, it is a challenge to design enforcers for which it is possible to give formal guarantees with respect to requirements, especially in the presence of typically largely varying environmental input (workload) per execution. Technically, an enforcement strategy can be formally modeled by a finite state machine (FSM) and the uncertain environment determining the workload by a discrete-time Markov chain. It has been shown in previous work that this formalization allows the formal verification of temporal properties (verification goals) regarding the fulfillment of requirements for a given enforcement strategy. In this article, we consider the so-far-unsolved problem of design space exploration and automatic synthesis of enforcement automata that maximize a number of deterministic and probabilistic verification goals formulated on a given set of non-functional requirements. For the design space exploration (DSE), an approach based on multi-objective evolutionary algorithms is proposed in which enforcement automata are encoded as genes of states and state transition conditions. For each individual, the verification goals are evaluated using probabilistic model checking. At the end, the DSE returns a set of efficient FSMs in terms of probabilities of meeting given requirements. As experimental results, we present three use cases while considering requirements on latency and energy consumption.

On-the-Fly Data Transformation in Action

Transactional and analytical database management systems (DBMS) typically employ different data layouts: row-stores for the first and column-stores for the latter. In order to bridge the requirements of the two without maintaining two systems and two (or more) copies of the data, our proposed system Relational Memory employs specialized hardware that transforms the base row table into arbitrary column groups at query execution time. This approach maximizes the cache locality and is easy to use via a simple abstraction that allows transparent on-the-fly data transformation. Here, we demonstrate how to deploy and use Relational Memory via four representative scenarios. The demonstration uses the full-stack implementation of Relational Memory on the Xilinx Zynq UltraScale+ MPSoC platform. Conference participants will interact with Relational Memory deployed in the actual platform.

The implementation of Shannon-limited polar codes-based information reconciliation for quantum key distribution

Quantum key distribution (QKD) gives a way to generate unconditionally secure keys for two remote users, Alice and Bob. Information reconciliation (IR), which can correct the errors caused by the imperfections of the QKD systems, is a critical component in QKD. Due to the high-security requirements and large volumes of data processing, robustness and efficiency are two main factors that must be considered for the implementation of IR. The polar codes-based IR has several potential advantages, such as capacity to reach Shannon-limit, high IR efficiency, and low computational complexity. Although CPU-based IR is always implemented in most of the previous works, it is not the optimal implementation in terms of performance and power dissipation. To the best of our knowledge, there is still no work to build a special-purpose hardware module for polar codes-based IR. In this paper, a dedicated design of hardware accelerator is first proposed for polar codes-based IR, in which the block-checked successive cancellation list (SCL) algorithm is used to verify the consistency of the sifted keys, and the overall failure probability of IR is significantly reduced. The proposed design is constructed into a partially-unrolled parallel architecture to accelerate the core decoder as well as balance the resource utilization. Furthermore, the hardware implementation is completed based on Xilinx Zynq UltraScale+ XCZU5EV MPSoC platform and achieves an IR throughput of 15 Mbps with a block length of 212, while less than of the amount of on-chip resources are used in other previous designs of SCL decoder. The proposed design can provide a real-time, low-cost solution for IR in QKD systems, and enhance the performance of QKD.

A High-Performance and Flexible Architecture for Accelerating SDN on the MPSoC Platform

Software-defined networking has been developing in recent years and the separation of the control plane and the data plane has made networks more flexible. Due to its flexibility, the software method is used to implement the data plane. However, with increasing network speed, the CPU is becoming unable to meet the requirements of high-speed packet processing. FPGAs are usually used as dumb switches to accelerate the data plane, with all intelligence centralized in the remote controller. However, the cost of taking the intelligence out of the switch is the increased latency between the controller and the switch. Therefore, we argue that the control decisions should be made as locally as possible. In this paper, we propose a novel architecture with high performance and flexibility for accelerating SDN based on the MPSoC platform. The control plane is implemented in the on-chip CPU and the data plane is implemented in the FPGA logic. The communication between the two components is performed using Ethernet communication. We design a high-performance TCAM based on distributed RAM. The architecture employs a pipeline design with modules connected via the AXI Stream interface. The designed architecture is flexible enough to support multiple network functions while achieving high performance at 100 Gbps. As far as we know, the architecture is the first proposed in the design of a 100 Gbps system.

An FPGA Based Energy-Efficient Read Mapper With Parallel Filtering and In-Situ Verification.

In the assembly pipeline of Whole Genome Sequencing (WGS), read mapping is a widely used method to re-assemble the genome. It employs approximate string matching and dynamic programming-based algorithms on a large volume of data and associated structures, making it a computationally intensive process. Currently, the state-of-the-art data centers for genome sequencing incur substantial setup and energy costs for maintaining hardware, data storage and cooling systems. To enable low-cost genomics, we propose an energy-efficient architectural methodology for read mapping using a single system-on-chip (SoC) platform. The proposed methodology is based on the q-gram lemma and designed using a novel architecture for filtering and verification. The filtering algorithm is designed using a parallel sorted q-gram lemma based method for the first time, and it is complemented by an in-situ verification routine using parallel Myers bit-vector algorithm. We have implemented our design on the Zynq Ultrascale+ XCZU9EG MPSoC platform. It is then extensively validated using real genomic data to demonstrate up to 7.8× energy reduction and up to 13.3× less resource utilization when compared with the state-of-the-art software and hardware approaches.

A High-Throughput Depth Estimation Processor for Accurate Semiglobal Stereo Matching Using Pipelined Inter-Pixel Aggregation

Semiglobal matching is an accurate stereo depth estimation algorithm, whereas implementing the high-throughput architecture has been challenging due to the inherent recursion on inter-pixel cost aggregation. Especially, the computation on horizontal scan pass is the critical path causing the throughput bottleneck. In this paper, we propose a new cluster-wise cost aggregation algorithm and its optimized architecture that enables to pipeline the inter-pixel aggregation and parallelize the scanline-level disparity computation. The proposed approach is performed not on every pixel but on each group of pixels, which significantly alleviates the timing constraint for the recursion. The disparity values at shifted multiple pixel positions are concurrently computed within a single clock period. We also propose the memory reduction scheme selecting a tiny number of informative values, which achieves 96% memory reduction compared to the straightforward approach storing overall values. The system-on-chip-based tiled processing scheme is employed, which allows the implementation without an external memory. The proposed architecture computes a depth map with 128 disparity levels at 103 frames per second on a full HD image on the Zynq ultrascale+ MPSoC platform, thus providing 2.6 times faster performance with a comparable accuracy compared to the state-of-the-art 8-path semiglobal matching implementation.

Co‐design implementation of High Efficiency Video Coding standard encoder on Zynq MPSoC

SummaryStatistical analysis of High Efficiency Video Coding (HEVC) encoder reveals that in the motion compensation block, the interpolation filter consumes more than 30% in the encoder time in comparison with other blocks. In this paper, we start with an optimized hardware implementation of the interpolation filter on field‐programmable gate array (FPGA) based on Xilinx setup environment. In a second step, a Hardware/Software (HW/SW) co‐design implementation of HM16.7 encoder is performed on Zynq MPSoC platform to evaluate the proposed interpolation filter IP in terms of total encoder run‐time, taking advantages of both processing units (quad‐core ARM Cortex TM‐A53 processor and Programmable Logic FPGA component) available on the Zynq MPSoC. The proposed architecture of luma and chroma filters was simulated and synthesized on Xilinx XCZU7EV‐2FFVC1156 FPGA at 250‐MHz clock frequency. The synthesis results present an optimized power consumption of 3.308 mW for higher resolutions (2560 × 1600 and 1920 × 1080) at 50 fps with the use of just 1% of the FPGA resources. The experimental results of the co‐design implementation of HEVC encoder present a speedup of 2 times (41% in PeopleOnStreet sequence) in terms of processing time compared to the software alone implementation, with a an increase of 0.51% of bit rate and a very small degradation of peak signal‐to‐noise ratio (PSNR) (0.01%).

A Configurable High Speed Crossbar Network on FPGA

The MPSoC platform plays a vital role in the design of parallel processor architectures. However, it poses a great challenge to design a configurable high-speed network regarding as the processors growing isomerization and reconfigurable. This paper proposes a configurable crossbar on-chip interconnection method based on FPGA, which can provide high speed high speed through Xilinx Fast Simplex Link (FSL) for processing elements include processors and hardware IP. We built a prototype system on FPGA to evaluate the transfer time and hardware costs of the crossbar network architectures. The experimental results show that each word can be reduced by 10 cycles, and the entire transmission delay only accounts for 6% of the total system operation time.

System Level Comparison of 3D Integration Technologies for Future Mobile MPSoC Platform

3D integration is being explored as a viable alternative to overcome limitations faced by mobile MPSoC platforms in traditional 2D designs. TSV based interdie connection is the most widely used approach currently. Although, TSV dimensions are scaling down, they still impose a restriction on the interdie connections density and the granularity at which 3D partitioning can be carried out. These limitations will aggravate in future scaled technologies. Alternatives such as Cu-Cu bonding need to be explored to achieve very fine-pitch and high density interdie connections. In this letter, we carry out a system architecture level comparison for a complex MPSoC platform instantiated for wireless PHY processing (WLAN and LTE). We compare 2D and 3D using: 1) TSVs with μ bump and RDL (F2B); and 2) Cu-Cu bonding (F2F). We show significant gains in 3D as compared to 2D. We also show that F2B and F2F have different system level architecture requirements, and that their impact on parameters at interconnect and system architecture level varies.

Run-time parallelization switching for resource optimization on an MPSoC platform

The recent development of multimedia applications on mobile terminals raised the need for flexible and scalable computing platforms that are capable of providing considerable (application specific) computational performance within a low cost and a low energy budget. The MPSoC with multi-disciplinary approach, resolving application mapping, platform architecture and runtime management issues, provides such multiple heterogeneous, flexible processing elements. In MPSoC, the run-time manager takes the design time exploration information as an input and selects an active Pareto point based on quality requirement and available platform resources, where a Pareto point corresponds to a particular parallelization possibility of the target application. To use system's scalability at best and enhance application's flexibility a step further, the resource management and Pareto point selection decisions need to be adjustable at run-time. This research work experiment run-time Pareto point switching for the MPEG-4 encoder. The work involves design time exploration and then embedding of two parallelization possibilities of the MPEG-4 encoder into one single component and enabling run-time switching between these parallelizations, to give run-time control over adjusting performance-cost criteria and allocation deallocation of hardware resources at run-time. The new system has the capability to encode each video frame with different parallelization. The obtained results offer a number of operating points on the Pareto curve in between the previous ones at sequence encoding level. The run-time manager can improve application performance up to 50 % or can save memory bandwidth up to 15 %, according to quality request.

A two-phase design space exploration strategy for system-level real-time application mapping onto MPSoC

In this paper, we present a two-phase design space exploration (DSE) approach to address the problem of real-time application mapping on a flexible MPSoC platform. Our approach is composed of two independent phases – analytical estimation/pruning and system simulation – communicating via a well-defined interface. The strength of the resulting strategy is twofold. On one hand, it is capable of combining the benefits of analytical models and simulation tools (i.e., speed and accuracy). And on the other hand, separating pruning and evaluation phases facilitates the integration of different or additional pruning techniques as well as other existing simulation tools. Finally, we also present several proof-of-concept DSE experiments to illustrate distinct aspects and capabilities of our framework. These experimental results reveal that our approach, compared to other approaches based only on analytical estimation models or simulations guided by e.g. genetic algorithms, not only can explore a large design space and reach a valid solution in a time-efficient way, but also can provide solutions optimizing resource usage efficiency, system traffic and processor load balancing.

A unified execution model for multiple computation models of streaming applications on a composable MPSoC

In this paper we propose a unified model of execution that aims to fill the abstraction level gap between the primitives of models of computation and the ones of an MPSoC. This model targets a composable MPSoC platform and supports the sequential, Kahn process networks, and dataflow models. Our model comprises of (1) execution operations implementing the primitives in the models of computation, and (2) a time model of execution of streaming applications on a composable platform. We implement these models of computation with the model of execution, and discuss the trade-offs involved. Case studies on an FPGA prototype of the composable MPSoC demonstrate how the model of execution actually works on a real platform. Furthermore they indicate that multiple applications modeled in KPN and dataflow run composably on the platform.

Adaptivity Support for MPSoCs Based on Process Migration in Polyhedral Process Networks

System adaptivity is becoming an important feature of modern embedded multiprocessor systems. To achieve the goal of system adaptivity when executing Polyhedral Process Networks (PPNs) on a generic tiled Network‐on‐Chip (NoC) MPSoC platform, we propose an approach to enable the run‐time migration of processes among the available platform resources. In our approach, process migration is allowed by a middleware layer which comprises two main components. The first component concerns the inter‐tile data communication between processes. We develop and evaluate a number of different communication approaches which implement the semantics of the PPN model of computation on a generic NoC platform. The presented communication approaches do not depend on the mapping of processes and have been implemented on a Network‐on‐Chip multiprocessor platform prototyped on an FPGA. Their comparison in terms of the introduced overhead is presented in two case studies with different communication characteristics. The second middleware component allows the actual run‐time migration of PPN processes. To this end, we propose and evaluate a process migration mechanism which leverages the PPN model of computation to guarantee a predictable and efficient migration procedure. The efficiency and applicability of the proposed migration mechanism is shown in a real‐life case study.

Service based communication for MPSoC platform- SegBus

MPSoC platforms offer solutions to deal with communication limitations for multiple cores on single chip, but many new issues arise within the context. The SegBus platform is one of the solutions for application deployment on multi-core applications. There are many applications where identical data is transferred from the same source towards different destinations. Multicast services may come as a performance improving factor for the interconnection platform, together with interrupt service. In this paper, the task is to analyze, how different services can be designed for the SegBus platform and observe the improvement in system performance. The designer can select the services according to the requirements. The running example is represented by the H.264 encoder. The SegBus platform architecture, the communication mechanism, the allocation of processing elements on the platform, the communication services and their implementation are the main topics elaborated here.

HW-SW Framework for Multimedia Applications on MPSoC: Practice and Experience

Constructing a intelligence surveillance system using embedded video server requires a sophisticated hardware/software framework for this system, and it should consider the performance, cost and energy/power consumption constrains. This paper discusses the design and implementation of an intelligence surveillance system which uses embedded multimedia server as core computing platform. We have carefully designed the embedded server based on MPSoC platform for the surveillance system whose key functionalities include heterogeneous multiprocessors environment set up, key algorithm porting and development framework design. The heterogeneous multiprocessors environment setup provides memory/communication management among multiprocessors to enhance the programmability of platform. Using realize/optimize the video encoding algorithm and porting to the TMS320DM6446 chip to guarantee the availability of media streaming system based on network. The hardware/software development framework provides an adequate mechanism which models signal processing in video surveillance system as process network and provides integrated homogeneous abstract programming environment. The proposed system has been implemented on an MPSoC platform and it is fully operational. The design principles of the whole system are validated with real experiments, and the performance characteristics are analyzed.

Multi-Core/Multi-IP Technology for Embedded Applications

SoC has driven the evolution of embedded systems or consumer electronics. Multi-core/multi-IP is the key technology to integrate many functions on a SoC for future embedded applications. In this paper, the transition of SoC and its required functions for cellular phones as an example is described. And the state-of-the-art multi-core technology of homogeneous type and heterogeneous type are shown. When many cores and IPs are integrated on a chip, collaboration between cores and IPs becomes important to meet requirement. To realize it, MPSoC Platform concept and elementary technology for this platform is described.

Automatic generation of embedded communication SW for heterogeneous MPSoC platforms

This paper addresses the problem of long design cycle of MPSoCs communication SW with automatic synthesis. The tool we propose takes as input a transaction level model (TLM) of MPSoC communication and outputs pin and cycle-accurate (PCA) bus drivers that can be linked to the synthesizable PCA model (PCAM). The TL communication is simple since TLM channels abstract away protocol details. PCAM communication, in turn, includes explicit definitions for each signal and pin. However, in most cases the TLMs are not suitable for implementation since they do not reflect the MPSoC platform. Usually the designers simulate (fast) TLMs, then manually implement PCA communication. Our communication SW synthesis transforms TL send and receive functions into platform specific PCAM bus drivers which can be automatically downloaded to the FPGA board. The presented results demonstrate the significant productivity gain achieved with our tool, with no great cost to either code size or system performance.

Buffer and Register Allocation for Memory Space Optimization

In today's embedded systems, memory hierarchy is rapidly becoming a major factor in terms of power, performance and area. This is especially true for embedded multimedia applications using temporary multi-dimensional arrays that are typically used to store intermediate results during multimedia processing. In this paper, we propose a new technique that optimizes the use of the cache and the registers. It consists in combining buffer and register allocation to reduce the size of the temporary arrays. Firstly we use the concept of live data to replace each array by a buffer of lower size. Then we replace references to these buffers by registers. The buffer allocation step keeps only useful data in memory and the register allocation step allows taking advantage of data reuse in internal loops. Codes considered in this paper are multimedia applications structured as a sequence of loop nests. The experiments are made on Unix environment and on the StepNP simulator (MPSoC platform of STMicroelctronics). They show that our technique yields significant reduction of the number of data cache and TLB misses.