MPEG-2 Video Decoder Research Articles

Parallelizing MPEG Decoder with Scalable Streaming Computation Kernels

In this paper, we describe a scalable and portable parallelized implementation of a MPEG decoder using a streaming computation paradigm, tailored to new generations of multi—core systems. A novel, hybrid approach towards parallelization of both new and legacy applications is described, where only data—intensive and performance—critical parts are implemented in the streaming domain. An architecture—independent StreamIt language is used for design, optimization and implementation of parallelized segments, while the developed StreamGate interface provides a communication mechanism between the implementation domains. The proposed hybrid approach was employed in re—factoring of a reference MPEG video decoder implementation; identifying the most performance—critical segments and re—implementing them in StreamIt language, with StreamGate interface as a communication mechanism between the host and streaming kernel. We evaluated the scalability of the decoder with respect to the number of cores, video frame formats, sizes and decomposition. Decoder performance was examined in the presence of different processor load configurations and with respect to the number of simultaneously processed frames.

Towards Generic Embedded Multiprocessing for RVC-CAL Dataflow Programs

Dataflow languages enable describing signal processing applications in a platform independent fashion, which makes them attractive in today's multiprocessing era. RVC-CAL is a dynamic dataflow language that enables describing complex data-dependent programs such as video decoders. To this date, design automation toolchains for RVC-CAL have enabled creating workstation software, dedicated hardware and embedded application specific multiprocessor implementations out of RVC-CAL programs. However, no solution has been presented for executing RVC-CAL applications on generic embedded multiprocessing platforms. This paper presents a dataflow-based multiprocessor communication model, an architecture prototype that uses it and an automated toolchain for instantiating such a platform and the software for it. The complexity of the platform increases linearly as the number of processors is increased. The experiments in this paper use several instances of the proposed platform, with different numbers of processors. An MPEG-4 video decoder is mapped to the platform and executed on it. Benchmarks are performed on an FPGA board.

Visitor-based application analysis methodology for early design space exploration

Applications and architectures for embedded systems are becoming more and more complex. It is difficult to analyze complex embedded applications at early stages of the design flow without generic automated tools and methodologies. Consequently, application analysis under the real input conditions is becoming more and more important. Existing application analysis methodologies mainly focus on a single design objective. A general purpose application analysis methodology is required to satisfy multiple objectives of early design space exploration. This article proposes a general purpose application analysis methodology based on a visitor design pattern. High level source specifications are transformed into a trace tree representation by dynamic analysis. Trace tree representation is analyzed by using a visitor design pattern to get run-time characteristics of the application. Among other outcomes, application characterization and average inherited parallelism are key concerns in this article. Experimental results with MPEG-2 video decoder shows viability of the proposed methodology.

System-level design optimization of reliable and low power multiprocessor system-on-chip

In this paper, we study the impact of application task mapping on the reliability of multiprocessor system-on-chip (MPSoC) application in the presence of soft errors. Based on this study, we propose a novel system-level design optimization of an MPSoC application through joint power minimization and reliability improvement. The power minimization is carried out using voltage scaling technique, while reliability improvement is achieved through careful choice of application task mapping on the homogeneous MPSoC processing cores. The overall aim is to minimize the number of single-event upsets (SEUs) experienced by the MPSoC application for suitably identified voltage scaling of the system processing cores such that the power is reduced and the specified real-time constraint is met. We evaluate the effectiveness of the proposed design optimization using a number of different applications, including MPEG-2 video decoder and synthetic applications. We show that for an MPEG-2 decoder with four processing cores, the proposed soft error-aware optimization produces a design with 38% less SEUs than soft error-unaware design optimization for an arbitrary soft error rate of 10−9, while consuming 9% less power and meeting a given real-time constraint. Furthermore, we investigate the impact of architecture allocation (allocation of processing cores) and show that for an MPSoC with six processing cores and a given real-time constraint, the proposed optimization produces design with up to 7% less SEUs compared to soft error-unaware designs at the cost of 5.5% higher power.

Reliability analysis of on-chip communication architectures: An MPEG-2 video decoder case study

In this paper, we present reliability analysis and comparison between on-chip communication architectures: dominant shared-bus AMBA and emerging Network-on-Chip (NoC); in the presence of single-event upsets (SEUs) using MPEG-2 video decoder as a case study. Employing SystemC-based fault simulations, reliability of the decoders is studied in terms of SEUs experienced in the computation cores and communication interconnects. We show that for a given soft error rate (SER), NoC-based decoder experiences lower SEUs than AMBA-based decoder. Using peak signal-to-noise ratio (PSNR) and frame error ratio (FER) metrics to evaluate the impact of SEUs at application-level, we show that NoC-based decoder gives up to 4 dB higher PSNR, while AMBA experiences up to 3% lower FER. Furthermore, we investigate the impact of routing, application task mapping (distribution of tasks among computation cores) and architecture allocation (choice of number of computation cores) on the reliability of the decoders in the presence of SEUs.

Communication architecture design for reconfigurable multimedia SoC platform

Memory and communication architecture have a significant impact on the performance, cost, and power of complex multiprocessor system-on-chip designs. In this paper, we present an automated bus matrix synthesis flow for efficient transaction-level design space exploration of communication architecture in a reconfigurable multimedia system-on-chip platform. Specifically, we consider hardware interface selection problem, which has significant effect on the overall cost of area and power. We propose a method to solve such hardware interface selection problem through static analysis of communication behavior. We experiment with JPEG encoder and H.264 encoder examples and the results show the reduction of area by 56.91% and power by 48.61% of bus matrix with 0.58% performance overhead on average compared to the case of maximum performance. According to our HW interface selection algorithm, we also experiment MPEG4 video decoder example. And the result is evaluated on the FPGA prototyping board.

Soft Error-Aware Voltage Scaling Technique for Power Minimization in Application-Specific Multiprocessor System-on-Chip

There is growing interest in evaluating the impact of soft errors on multiprocessor system-on-chip (MPSoC) at application-level rather than architectural-level, particularly in multimedia applications to optimize system design. This has recently led to the concept of application-level correctness. In this paper, we consider the relationship between application-level correctness and system-level power management using voltage scaling technique with the aim to generate designs that are optimized in terms of power consumption, while providing acceptable application-level correctness and meeting real-time performance deadlines. We propose a novel voltage scaling technique based on linear programming capable of identifying the appropriate supply voltage and frequency values of the processing cores in an MPSoC such that the power consumption is minimized for a given soft error rate (SER) and a specified performance deadline. We evaluate the effectiveness of our technique using an MPEG-2 video decoder as a case study and with peak signal-to-noise ratio (PSNR) as the application-level correctness metric. We show that the proposed voltage scaling technique can achieve up to 85% power reduction for SER of 3.98E?8, while maintaining acceptable levels of real-time performance (29 frames/s) and application-level correctness (30dB PSNR). The above case study is based on an MPSoC architecture with four processing cores. We have also investigated the effect of varying the number of processing cores (architecture allocation) and application task mapping (distribution of tasks among cores of the MPSoC architecture) on the trade-offs between application-level correctness and power consumption minimization using the proposed voltage scaling technique.

A Low-overhead Scheduling Methodology for Fine-grained Acceleration of Signal Processing Systems

Fine-grained accelerators have the potential to deliver significant benefits in various platforms for embedded signal processing. Due to the moderate complexity of their targeted operations, these accelerators must be managed with minimal run-time overhead. In this paper, we present a methodology for applying flow-shop scheduling techniques to make effective, low-overhead use of fine-grained DSP accelerators. We formulate the underlying scheduling approach in terms of general flow-shop scheduling concepts, and demonstrate our methodology concretely by applying it to MPEG-4 video decoding. We present quantitative experiments on a soft processor that runs on a field-programmable gate array, and provide insight on trends and trade-offs among different flow-shop scheduling approaches when applied to run-time management of fine-grained acceleration.

Mapping of nomadic multimedia applications on the ADRES reconfigurable array processor

This paper introduces the mapping of MPEG video decoders on ADRES, IMEC’s new coarse-grain reconfigurable and fully C-programmable array processor that targets nomadic devices. ADRES is a flexible template that allows the instantiation of many different processor versions. An XML-based architecture description language allows a designer to easily generate different processor instances with full compiler support by specifying different values for the communication topology, the number and size of local register files and functional units and supported instruction set. ADRES supports a VLIW-like programming model with a pure VLIW mode for legacy code, and a (coarse-grain reconfigurable) array mode with very high parallelism for the processing of compute intensive loops. We demonstrate the mapping of two video decoders MPEG-2 and AVC, and discuss the performance trade-offs for two critical kernels: IDCT and integer transform. As a result, an ADRES based system can perform AVC decoding in CIF resolution with less then 50 MHz on a 4 × 4 array processor.

Frame Buffer Access Reduction for MPEG Video Decoder

Frame buffer power consumption and bandwidth requirement are two critical design issues in MPEG video decoders due to the overwhelming amount of frame data accesses. This paper proposes a reusable macroblock detector (RMD) which exploits the characteristic of a stationary macroblock (MB) to identify the reusable MBs in the frame buffer and avoid unnecessary data transfers. The RMD on average reduces about one quarter of the frame buffer accesses for 18 video sequences.

Stochastic Modeling and Optimization for Energy Management in Multicore Systems: A Video Decoding Case Study

This paper presents a novel stochastic modeling and optimization framework for energy minimization in multicore systems running real-time applications with tolerance to deadline misses. This framework is based on stochastic application models, which capture the variability of and the spatial and temporal correlations among the workloads of concurrent and interdependent tasks that constitute the application. These stochastic models are utilized in novel mathematical formulations to obtain optimal energy management policies. Experimental results on MPEG2 video decoding show that significant energy savings can be achieved, often close to the theoretical upper bound.

Sinus of Valsalva Aneurysm with Dissection into the Interventricular Septum

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QoS-supported On-chip Communication for Multi-processors

We present a Quality of Service (QoS)-supported on-chip communication that increases the shared communication resources for multi-processor systems on chip. Time-critical embedded systems require tight guaranteed services in terms of throughput, latency etc. in order to comply to hard real-time constraints. Typically, guaranteed-service schemes require dedicated/reserved resources (i.e. links) for communication and thus suffer from low resource utilization. So improving the bandwidth utilization by using the unused bandwidth among the other competing transactions in a fair fashion is an important issue. To the best of our knowledge, we are presenting the first approach for on-chip communication that provides a high resource utilization under a transaction-specific, flexible communication scheme. It provides tight time-related guarantees through our bounded arbitration scheme considering the lower and the upper bounds for each type of transactions. We demonstrate its advantages by means of a complete MPEG4 video decoder case study analysis and achieve under certain constraints a bandwidth utilization of up to 100% and 97% on average with a guaranteed 100% bandwidth. Thus, we provide an on-chip communication scheme that provides high bandwidth uti lization while providing tight guarantee.

A 125 $\mu{\hbox{W}}$, Fully Scalable MPEG-2 and H.264/AVC Video Decoder for Mobile Applications

A low-power dual-standard video decoder has been developed for mobile applications. It supports MPEG-2 SP@ML and H.264/AVC BL@L4 video decoding in a single chip and features a scalable architecture to reach area/power efficiency. This chip integrates diverse algorithms of MPEG-2 and H.264/AVC to reduce silicon area. Three low-power techniques are proposed. First, a domain-pipelined scalability (DPS) technique is used to optimize the pipelined structure according to the number of processing cycles. Second, bandwidth scalability is implemented via a line-pixel-lookahead (LPL) scheme to improve the external bandwidth and reduce the internal memory size, leading to 51% of memory power reduction compared to a conventional design. Third, low-power motion compensation and deblocking filter are designed to reduce the operating frequency without degrading system performance. A test chip is fabricated in a 0.18mum one-poly six-metal CMOS technology with an area of 15.21 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . For mobile applications, H.264/AVC and MPEG-2 video decoding of quarter-common intermediate format (QCIF) sequences at 15 frames per second are achieved at 1.15 MHz clock frequency with power dissipation of 125 muW and 108 muW, respectively, at 1V supply voltage

Hybrid error concealments based on block content

We present a novel error-concealment method for MPEG-2 video decoders. Imperfect transmission of block-based compressed images may result in the loss of blocks, degrading the quality of the received video signal. Since an I-picture is used as a reference picture for forward and backward predictions of neighbouring pictures, transmission errors in an I-picture are propagated both spatially in the I-picture and temporally to P-/B-pictures, and thus may severely degrade the video signal, compared with the errors in P-/B-pictures. To minimise the quality degradation of the video signal, error concealment has been performed in I-pictures through adaptive spatial and temporal interpolations in the respective domains. Using edge information extracted from the neighbourhoods of the erroneous macroblocks, we categorise each erroneous macroblock (MB) based on the characteristics of neighbouring MBs. The categorised MB is reconstructed by the spatial or temporal error concealment methods selected by the category-dependent criteria reflecting the properties of the block content. The proposed technique solves blocky artefacts and blurring problems of existing error concealment methods and thus effectively conceals the lost blocks in an error video signal. Through computer simulations on damaged images, we show that the proposed method is robust to image characteristics and obtains better subjective quality than other error concealment methods.

FPGA-oriented HW/SW implementation of the MPEG-4 video decoder

This paper presents an FPGA-oriented implementation methodology for the MPEG-4 video decoder based on a hardware/software co-design approach. The MPEG-4 decoder is based on MoMuSys optimized reference software combined with new hardware VLSI architectures. New architectures for input demultiplexing, variable length decoding and inverse discrete cosine transform are developed. All software and hardware structures are evaluated in terms of visual quality, computational complexity and memory bandwidth metrics. The presented implementation is compared with an optimized reference software-based solution. Simulation results demonstrate a reduction of decoder complexity, especially speed and memory bandwidth, while maintaining an acceptable quality of decoded sequences. The proposed hardware additions provide 30% speed improvement over software solution, thereby reducing the clock rate required to process full-rate video from 300 MHz down to 213 MHz. The MPEG-4 decoder was functionally tested on a Flextronics FPGA prototyping board.

Realization of Embedded Multimedia System Based On Dual-Core Processor OMAP5910

This paper focuses on the realization of a complete embedded system using the dual-core processor OMAP5910. Detailed description of how to compose the hardware system is presented with a description of the software system on our platform. Tasks communication between the two cores is realized using the DSP driver. The system bootloader and the DSP bootloader are described in detail. The implementation of the MPEG-4 video decoder has been realized on the presented system. Higher speed can be achieved and less power is needed for MPEG-4 video processing on the dual-core platform. This dual-core system can be applied to 3G wireless communication, robot control and vision systems.

A DSP based IP set-top box for home entertainment

In this paper, the implementation of a digital signal processor (DSP) based Internet protocol set-top box for home entertainment networks is described. The main functional blocks are the MPEG-2 transport stream demultiplexer, the audio and video decoders and the audio and video display management modules (with on-screen display capabilities). All blocks have been built into a single low-cost DSP to allow multi-format operation in the future. A prototype has been designed and fully tested in a real environment.

Cache modeling and optimization for portable devices running MPEG-4 video decoder

There are increasing demands on portable communication devices to run multimedia applications. ISO (an International Organization for Standardization) standard MPEG-4 is an important and demanding multimedia application. To satisfy the growing consumer demands, more functions are added to support MPEG-4 video applications. With improved CPU speed, memory sub-system deficiency is the major barrier to improving the system performance. Studies show that there is sufficient reuse of values for caching that significantly reduce the memory bandwidth requirement for video data. Software decoding of MPEG-4 video data generates much more cache-memory traffic than required. Proper understanding of the decoding algorithm and the composition of its data set is obvious to improve the performance of such a system. The focus of this paper is cache modeling and optimization for portable communication devices running MPEG-4 video decoding algorithm. The architecture we simulate includes a digital signal processor (DSP) for running the MPEG-4 decoding algorithm and a memory system with two levels of caches. We use VisualSim and Cachegrind simulation tools to optimize cache sizes, levels of associativity, and cache levels for a portable device decoding MPEG-4 video.

An Efficient Embedded Bitstream Parsing Processor for MPEG-4 Video Decoding System

In this paper, the bitstream parsing analysis and an efficient and flexible bitstream parsing processor are presented. The bitstream parsing analysis explores the critical part in bitstream parsing. Based on the result, the novel approaches to parse data partitioned bitstreams are presented. An efficient instruction set optimized for bitstream processing, especially for DCT coefficient decoding, is designed and the processor architecture can be programmed for various video standards. It has been integrated into an MPEG-4 video decoding system successfully and can achieve real time bitstream decoding with bitstream coded under 4CIF frame size with 30 fps, 8Mbps, which is the specification of MPEG-4 Advanced Simple Profile Level 5.