MPEG-2 Video Encoder Research Articles

Human visual perception‐based localized backlight scaling method for high dynamic range LCDs

AbstractThis paper presents a backlight control algorithm for liquid crystal display devices, which considers the human visual properties that we are usually attracted to the saliencies in a scene. The saliency means regions or objects that have different contrast or color from the surrounding, and thus attract our attention, which can be measured in various ways from each pixel value and its relation with the surrounding ones. Hence, by keeping or boosting the backlight of salient regions while suppressing in others, the quality of salient regions and overall contrast are enhanced. In addition, power can be saved by backlight dimming in non‐salient regions, without loss of overall quality in terms of human visual perception. In this backlight control process, the amount of energy consumption is regulated so that the proposed method consumes less than or equal energy as before, by developing a power management algorithm based on the bit rate control strategies of MPEG2 video encoders. Precisely, the energy consumption in each backlight unit is controlled by a parameter, so that the sum of energies of overall backlight units is kept within a limit.

Cryptanalysis of a video encryption method based on mixing and permutation operations in the DCT domain

Wireless sensor network (WSN) needs efficient and secure and simple algorithms to be implemented in order to assure confidential communications between nodes and base station. The most suitable kind of algorithm seems to be the partial encryption ciphers. MPEG video encryption can be done by selecting the most significant parts of this sequence which are the group of pictures known as the I-frames. In this letter, we study the security of a partial video encryption method by Yang and Sun (Prog Nat Sci 18:1299–1304, 2008) that can be used in video nodes in a WSN. Based on the given analysis, it is demonstrated that the cryptosystem under study has serious weaknesses in the shuffling and the mixing processes which makes it vulnerable to chosen plaintext attack. Through the studied cipher, we question whether practitioners should design their own new ciphers for their specific applications or should they use well-known ciphers and fit them to their applications.

A scheduler synthesis methodology for joint SW/HW design exploration of SoC

The introduction of high-performance applications such as multimedia applications into SoCs led the manufacturers to provide embedded SoCs able to offer an important computing power which makes it possible to answer the increasing requirements of future evolutions of these applications. One of the adopted solutions is the use of multiprocessor SoCs. In this paper, we present a joint SW/HW design exploration methodology for multiprocessor SoCs. The system model relies on transaction-level component-based models for modeling parallel software and multiprocessor hardware. Our proposal comprises two original points. First, we propose a composable software-level scheduler constraints synthesis technique. Second, we present a combined software-level and exploratory hardware-level schedulers. The methodology has the advantage of combining real-time requirements of software with effective exploitation of multiprocessor hardware. We describe and apply the methodology to synthesize a scheduler of a slice-based MPEG-4 video encoder on the multiprocessor Cake SoCs.

Extraction of Desired Partial Block of a Frame from MPEG Video Stream

In MPEG video encoding, the next frame is encoded based on the previous frame. For forward replay of the video, extraction of data of the next frame from the current frame is a trivial process. However, for backward replay, it may not always be possible to extract data of the next (previous) frame completely from the currently displayed frame. In this paper, we propose a method for extracting unpredictable portion of a frame from MPEG video. This helps in extracting the desired portion rather than decoding the entire frame.

Modelling and Simulation of Adaptive Buffer Management Mechanism Using Nested Autoregressive Process-Based Mpeg-Encoded Traffic Model

High speed networks provide real-time variable bit rate (VBR) service with diversified traffic flow characteristics and quality requirements. The VBR traffic has stringent delay and packet loss requirements. The burstiness of the correlated traffic makes dynamic management highly desirable to satisfy the Quality of Service (QoS) requirements. Buffer management in queueing systems plays important role towards effective control of QoS for various types of applications. In this paper, ADaptive Partial Buffer Sharing (ADPBS) scheme for priority queueing system is proposed and analyzed. The input to the queue has been taken using auto-regressive (AR) process of order 2 for MPEG-encoded VBR video traffic. The results of simulations indicate that dynamically controlled threshold in ADPBS contributes in reducing the packet loss of different priority classes as compared with static partial buffer sharing queue and first-in first-out queue based on threshold control parameters and the traffic type.

MODELLING AND SIMULATION OF ADAPTIVE BUFFER MANAGEMENT MECHANISM USING NESTED AUTOREGRESSIVE PROCESS-BASED MPEG-ENCODED TRAFFIC MODEL

AbstractHigh speed networks provide real-time variable bit rate (VBR) service with diversified traffic flow characteristics and quality requirements. The VBR traffic has stringent delay and packet loss requirements. The burstiness of the correlated traffic makes dynamic management highly desirable to satisfy the Quality of Service (QoS) requirements. Buffer management in queueing systems plays important role towards effective control of QoS for various types of applications. In this paper, ADaptive Partial Buffer Sharing (ADPBS) scheme for priority queueing system is proposed and analyzed. The input to the queue has been taken using auto-regressive (AR) process of order 2 for MPEG-encoded VBR video traffic. The results of simulations indicate that dynamically controlled threshold in ADPBS contributes in reducing the packet loss of different priority classes as compared with static partial buffer sharing queue and first-in first-out queue based on threshold control parameters and the traffic type.

Directional diamond motion estimation algorithm based on parallelism and prediction

The motion estimation algorithm in the MPEG-4 video encoding was studied and the potential parallelism in the algorithm was analyzed.Then the multi-core parallel computing concept was used in the directional diamond searching algorithm,and a prediction mechanism was introduced to improve the degree of parallelism.Then the directional diamond Motion estimation algorithm based on parallelism and prediction(PPDDME) was proposed.The experimental results coming from PC and the Omap5910 embedded platform show that the encoding speed is improved efficiently and the compression quality is the same as the serial algorithm.

MPEG video encryption algorithm based on Lorenz chaotic system

An encryption algorithm which combined the process of MPEG video compressing with video encryption based on Lorenz chaotic system was put forward to deal with the security problem of video information. Three dimensional chaotic sequences of Lorenz system were used to encrypt DC, AC and motion vector coefficients during the compressing of I frame, B frame and P frame. The luminance information of I frame was encrypted among blocks by the chaotic sequence. The algorithm is secure and real-time because the encryption is done during the process of video compressing.

An Efficient Framework for Configurable Video Encoder

The implementation of real-time video coding systems with limited resources such as memory volume and CPU speed is a challenging task. In this paper, an efficient embedded multi-modal MPEG-4 video encoder (EMVC) is proposed and implemented to meet the requirement of encoding different modals (colors, resolutions, and bandwidths) video in size and power-restricted scenario. The hardware framework of EMVC is based on FPGA and DSP, which takes full advantage of the strongpoint of DSP and FPGA—powerful digital signal processing ability of DSP is utilized to complete most of the complex video coding, and flexible configuration, the parallelism and high speed of FPGA cooperates to accomplish logical control and auxiliary functions in video coding. The hardware framework is designed with strong processing ability, flexible configuration, and extensive coverage. In software design, we first improve some key algorithms in MPEG-4 standard that have great impact on coding efficiency, a fast motion estimation algorithm—smooth motion vector field adaptive search technique (SMVFAST) and a DSP-based efficient quantization computation method—EQ4DSP are put forward respectively; second, according to the characters of DSP's hardware resource, the encoder software is optimized at system and code levels. At the system level, EDMA (Enhanced Direct Memory Access) channels in DSP are used to parallel the data transfer, and the software structure of the video encoders is changed from frame-based to GMB-based (Group of Macro-Block) to make use of the parallel processing capacity of DSP. At code level, the codes of the frequently called modules in the encoder are the critical optimized part, and the main code optimization methods used in EMVC include: using an intrinsic function to replace the complicated C/C++ code, using packed data processing to maximize the data throughput, unrolling the loop to increase software pipelines, translating C code to Linear Assembly, and so on. By making use of the reserved user-data field in the MPEG-4 standard syntax, a multi-modal function of EMVC is realized, namely, the system can switch among 720 × 576 and 352 × 288 resolutions, grey and color video, 2 M and 256 K bandwidth. Moreover, the mode switch can be achieved in real time according to the input control command. Experimental results show that EMVC not only runs efficiently but also has good flexibility and generality. Furthermore, by realizing diverse video or image coding algorithms, it can also satisfy the requirements of various embedded video applications, especially those with strict restriction in size, power consumption, and control flexibility.

Symbolic quality control for multimedia applications

We present a fine grain quality control method for multimedia applications. The method takes as input an application software composed of actions. The execution times of actions are unknown increasing functions of quality level parameters. The method allows the construction of a Controller which computes adequate action schedules and corresponding quality levels, so as to meet QoS requirements for a given platform. These include requirements for safety (action deadlines are met) as well optimality (maximization and smoothness of quality levels).The Controller consists of a Quality Manager and a Scheduler. For each action, the Controller uses a quality management policy for choosing a schedule and quality levels meeting the QoS requirements. The schedule is selected amongst a set of optimal schedules computed by the Scheduler.We extend and improve results of previous papers providing a solid theoretical basis for designing and implementing the Controller.We propose a symbolic quality management method using speed diagrams, a representation of the controlled system’s dynamics. Instead of numerically computing a quality level for each action, the Quality Manager changes action quality levels based on the knowledge of constraints characterizing control relaxation regions. These are sets of states in which quality management for a given number of computation steps can be relaxed without degrading quality.We study techniques for efficient computation of optimal schedules.We present experimental results including the implementation of the method and benchmarks for an MPEG4 video encoder. The benchmarks show drastic performance improvement for controlled quality with respect to constant quality. They also show that symbolic quality management allows significant reduction of the overhead with respect to numeric quality management. Finally, using optimal schedules can lead to considerable performance gains.

Exploiting the Expressiveness of Cyclo-Static Dataflow to Model Multimedia Implementations

The design of increasingly complex and concurrent multimedia systems requires a description at a higher abstraction level. Using an appropriate model of computation helps to reason about the system and enables design time analysis methods. The nature of multimedia processing matches in many cases well with cyclo-static dataflow (CSDF), making it a suitable model. However, channels in an implementation often use for cost reasons a kind of shared buffer that cannot be directly described in CSDF. This paper shows how such implementation specific aspects can be expressed in CSDF without the need for extensions. Consequently, the CSDF graph remains completely analyzable and allows reasoning about its temporal behavior. The obtained relation between model and implementation enables a buffer capacity analysis on the model while assuring the throughput of the final implementation. The capabilities of the approach are demonstrated by analyzing the temporal behavior of an MPEG-4 video encoder with a CSDF graph.

Application-Specific Data Path for Highly Efficient Computation of Multistandard Video Codecs

A novel mechanism that flexibly adapts data flows and configures computational units is proposed to establish an application-specific data path in the digital signal processor (DSP) that can efficiently perform multistandard video codecs. Based on this mechanism, the proposed application-specific data path, using the very long instruction word (VLIW) architecture with eight computational units of five arithmetic logic units (ALUs), one multiplier and two load/store units, is designed to perform five adaptive operations according to the characteristics of the low-level functions of MPEG-2, MPEG-4 and H.264/AVC video codecs. Using these adaptive operations, the proposed application-specific data path reduces the number of clock cycles required by the TI TMS320C64x data path to perform the low-level functions of the MPEG-2 video encoder and the H.264/AVC video decoder by 23.10% and 28.43%, respectively, for 30 352times288-pixel Foreman frames. Additionally, considering the operating frequency, the proposed application-specific data path reduces the computation time required by the TI TMS320C64x data path to realize the abovementioned encoder and decoder by 19.86% and 25.41%, respectively. Based on the TSMC 0.18-mum CMOS cell library, the proposed application-specific data path is implemented, and exhibits the highest ratio of computational power to hardware cost among all of the data paths associated with the conventional DSPs in implementing the low-level functions of video codecs

Parallel programming models for a multiprocessor SoC platform applied to networking and multimedia

The MultiFlex system is an application-to-platform mapping tool that integrates heterogeneous parallel components-H/W or S/W- into a homogeneous platform programming environment. This leads to higher quality designs through encapsulation and abstraction. Two high-level parallel programming models are supported by the following MultiFlex platform mapping tools: a distributed system object component (DSOC) object-oriented message passing model and a symmetrical multiprocessing (SMP) model using shared memory. We demonstrate the combined use of the MultiFlex multiprocessor mapping tools, supported by high-speed hardware-assisted messaging, context-switching, and dynamic scheduling using the StepNP demonstrator multiprocessor system-on-chip platform, for two representative applications: 1) an Internet traffic management application running at 2.5 Gb/s and 2) an MPEG4 video encoder (VGA resolution, at 30 frames/s). For these applications, a combination of the DSOC and SMP programming models were used in interoperable fashion. After optimization and mapping, processor utilization rates of 85%-91% were demonstrated for the traffic manager. For the MPEG4 decoder, the average processor utilization was 88%

Scalable MPEG-4 Encoder on FPGA Multiprocessor SOC

High computational requirements combined with rapidly evolving video coding algorithms and standards are a great challenge for contemporary encoder implementations. Rapid specification changes prefer full programmability and configurability both for software and hardware. This paper presents a novel scalable MPEG-4 video encoder on an FPGA-based multiprocessor system-on-chip (MPSOC). The MPSOC architecture is truly scalable and is based on a vendor-independent intellectual property (IP) block interconnection network. The scalability in video encoding is achieved by spatial parallelization where images are divided to horizontal slices. A case design is presented with up to four synthesized processors on an Altera Stratix 1S40 device. A truly portable ANSI-C implementation that supports an arbitrary number of processors gives 11 QCIF frames/s at 50 MHz without processor specific optimizations. The parallelization efficiency is 97% for two processors and 93% with three. The FPGA utilization is 70%, requiring 28 797 logic elements. The implementation effort is significantly lower compared to traditional multiprocessor implementations.

Adjusting forward error correction with temporal scaling for TCP-friendly streaming MPEG

New TCP-friendly constraints require multimedia flows to reduce their data rates under packet loss to that of a conformant TCP flow. To reduce data rates while preserving real-time playout, temporal scaling can be used to discard the encoded multimedia frames that have the least impact on perceived video quality. To limit the impact of lost packets, Forward Error Correction (FEC) can be used to repair frames damaged by packet loss. However, adding FEC requires further reduction of multimedia data, making the decision of how much FEC to use of critical importance. Current approaches use either inflexible FEC patterns or adapt to packet loss on the network without regard to TCP-friendly data rate constraints. In this article, we analytically model the playable frame rate of a TCP-friendly MPEG stream with FEC and temporal scaling, capturing the impact of distributing FEC within MPEG frame types with interframe dependencies. For a given network condition and MPEG video encoding, we use our model to exhaustively search for the optimal combination of FEC and temporal scaling that yields the highest playable frame rate within TCP-friendly constraints. Analytic experiments over a range of network and application conditions indicate that adjustable FEC with temporal scaling can provide a significant performance improvement over current approaches. Extensive simulation experiments based on Internet traces show that our model can be effective as part of a streaming protocol that chooses FEC and temporal scaling patterns that meet dynamically-changing application and network conditions.

A perceptual two-pass VBR MPEG-2 video encoder

This paper presents a perceptual two-pass VBR MPEG-2 video encoder suitable for digital storage applications. The proposed algorithm aims to achieve perceptually uniform distortion among adjacent macroblocks within a frame and smoothen the inter-frame visual quality fluctuation as soon as possible. In the first-pass coding, we analyze the video sequence and collect some useful coding parameters to accurately measure the frame coding complexity. In the second-pass coding, the target bits are allocated to all frames optimally according to the coding complexity, certainly with decoder buffer considered. The human visual system characteristics including both the spatial and temporal masking effects are employed to improve the proposed adaptive quantization algorithm. Furthermore, an improved iteration based Qp selection algorithm is proposed to search for the optimal frame-level reference Qp resulting in satisfactory iteration speed and iteration precision. Experimental results show that the proposed algorithm can achieve superior visual quality both objectively and subjectively compared with the reference algorithms.

Pipelined Scheduling of Functional HW/SW Modules for Platform-Based SoC Design

We developed a pipelined scheduling technique of functional hardware and software modules for platform-based system-on-a-chip (SoC) designs. It is based on a modified list scheduling algorithm. We used the pipelined scheduling technique for a performance analysis of an MPEG4 video encoder application. Then, we applied it for architecture exploration to achieve a better performance. In our experiments, the modified SoC platform with 6 pipelines for the 32-bit dual layer architecture shows a 118% improvement in performance compared to the given basic SoC platform with 4 pipelines for the 16-bit single-layer architecture.

Memory centric design of an MPEG-4 video encoder

The cost-efficient implementation of video codecs requires a set of methodologies and decision taking at different levels in the design flow. We combine upfront algorithmic tuning with memory centric optimizations to transform the video application into a system consisting of functional blocks with localized data processing and a tailored memory hierarchy. This memory optimized functional description is the leverage for the cost-efficient mapping of the system on integrated multimedia platforms. It closely reflects the real implementation constraints and consequently allows for steering the architecture selection in a correct way. The proposed approach is demonstrated on a MPEG-4 video encoder and leads to its implementation as a pipelined system. Hardware development of the motion estimation validates that the high-level memory centric concepts are applicable and realizable at the lowest level. The motion estimation kernel supports up to 30 CIF f/s with minimized processing element requirements and data input rates.

MPEG-encoded variable bit-rate video traffic modelling

Video streaming and conferencing are expected to be the major services in future communication systems. The design of communication systems to support high-quality video services requires the characterisation and modelling of video traffic. An accurate video traffic model for MPEG encoded video traffic proposed. An analysis of MPEG-encoded video traffic shows that I, P and B frame sizes within the same scene are cross-correlated. However, existing frame-level video traffic models often ignore this correlation. In contrast, a new model utilising the multinomial method (MM) is presented to capture this cross-correlation. The MM is used together with the spatial renewal process (SRP) to model MPEG-encoded VBR video traffic. The model is called SRP-MM. In addition the MM is utilised to enhance the existing model, the nested-autoregressive (nested-AR). The enhanced model is called nested-AR-MM. Simulation results demonstrate that the proposed models, the SRP-MM and nested-AR-MM, predict the empirical frame-size marginal distribution, autocorrelation and queuing performance closely. The nested-AR and fractional autoregressive integrated moving average (FARIMA) models from the existing literature are also implemented for comparison. It is shown that the proposed models outperform both nested-AR and FARIMA.

Multi-Resolution Block Matching Algorithm and Its VLSI Architecture for Fast Motion Estimation in an MPEG-2 Video Encoder

This paper proposes a high-performance multi-resolution motion estimation algorithm (HMRME) for MPEG-2 video encoding, which satisfies high estimation performance and efficient very large scale integration (VLSI) implementation. HMRME is based on a characteristic that field motion vectors (MVs) are very similar to their corresponding frame MV. Firstly, HMRME performs frame-based motion estimation (ME) as follows: at the coarsest level, two MV candidates are found on the basis of minimum matching error. The two MV candidates from the coarsest level search and the other one based on spatial MV correlation are used as center points for three local searches at the middle level. At the finest level, a frame MV is obtained from a local search around a single candidate from the middle level search. Field MVs are estimated with the single MV candidate from the middle level search of frame ME as initial estimates at the finest level, without any coarser level searches. This paper also describes a VLSI architecture based on HMRME. This architecture is designed to provide a good tradeoff between on-chip memory size and I/O bandwidth with high throughput. We implemented this architecture with about 140 K gates and 2.5 K bytes static random access memory for a large search range of [-192.0, +191.5] by using a synthesizable Verilog HDL.