MPEG-2 Decoder Research Articles

A Design of the Media Processing Unit for a Multimedia Communication Terminal

In this paper, we propose a new architecture, and its implementation, for the media-processing unit of the set-top unit (STU) in ETRI's video-on-demand (VOD) system, Interactive Multimedia exPRESS (IMPRESS). The STU in our system has MPEG-2 video quality in movie-on-demand, but low quality in bidirectional communication when considering implementation cost. The media processing unit in our STU consists of three parts: one is system control module, which has a reduced instruction set computing (RISC) processor and controls the overall functions of the unit; another is an MPEG-2 decoder module, which decodes MPEG-2 transport stream (TS) in realtime and presents the contents; and the third is an audio/video communication module, which enables bidirectional video-conferencing.

Single Chip Dual---Issue RISC Processor for Real---Time MPEG---2 Software Decoding

A single chip system for real–time MPEG–2 decoding can be created by integrating a general purpose dual–issue RISC processor, with a small dedicated hardware for the variable length decoding (VLD) and block loading processes; a 32KB instruction RAM; and a 32KB data RAM. The VLD hardware performs Huffman decoding on the input data. The block loader performs the half–sample prediction for motion compensation and acts as a direct memory access (DMA) controller for the RISC processor by transferring data between an external 2MB DRAM and the internall 32 KB data RAM. The dual-issue RISC processor, running at 250MHz, is enhanced with a set of key sub-word and multimedia instructions for a sustained peak performance of 1000 MOPS. With this setup for MPEG-2 decoding applications, bi-directionally predicted non-intra video blocks are decoded in less than 800 cycles, leading to a single-chip, real-time MPEG-2 decoding system.

An MPEG decoder with embedded compression for memory reduction

We present an MPEG decoder with reduced system costs by employing embedded compression of the reference frames which are used for motion compensated (MC) decoding. The embedded compression scheme used is based on either block predictive coding or DCT transform coding, depending on the required memory compression. The compression features simple recovery of (MC) block data, while preventing visible artifacts. The compression was optimized for low costs, enabling real application in a commercial MPEG IC. It was found that the same techniques can be applied in the encoder as well.

A 1.2-W, 2.16-GOPS/720-MFLOPS embedded superscalar microprocessor for multimedia applications

We have designed a microprocessor that is based on a single instruction multiple data stream (SIMD) architecture. It features a two-way superscalar architecture for multimedia embedded systems that need to support especially MPEG2 video decoding/encoding and 3DCG image processing. This microprocessor meets all requirements of embedded systems, including (a) MPEG2 (MP@ML) decoding and graphic processing capabilities for three-dimensional images, (b) programming flexibility, and (c) low power consumption and low manufacturing cost. High performance was achieved by enhanced parallel processing capabilities while adopting a SIMD architecture and a two-way superscalar architecture. Programming flexibility was increased by providing 170 dedicated multimedia instructions. Low power consumption was achieved by utilizing advanced process technology and power-saving circuits. The processor supports a general-purpose RISC instruction set. This feature is important, as the processor will have to work as a controller of various target systems. The processor has been fabricated by 0.21-/spl mu/m CMOS four-metal technology on a 9.84/spl times/10.12 mm die. It performs 2.16 GOPS/720 MFLOPS at an operating frequency of 180 MHz, with a power consumption of 1.2 W and a power supply of 1.8 V.

DVB integrated satellite receiver decoder PC card

This paper deals with an extension card which upgrades a personal computer (PC) for the reception and processing of DVB (digital video broadcasting)compliant satellite signals. It includes the MPEG-2 decoding and the video representation in a window of the graphical user interface by means of a high quality video overlay technique. A variety of hardware and software interfaces allows the adaptation to a wide range of applications.

A free time-shift DVD video recorder

A DVD video recorder is proposed that frees viewers from restrictions on when a program can be viewed by allowing a program to be played while the recorder continues to record other programs. This recorder also makes recording, viewing, searching and managing programs much easier than with a conventional VCR. The recorder consists of two MPEG1+ video encoders, one MPEG2 decoder, a DVD drive with a disk changer, and a hard-disk-drive.

A bus-monitoring model for MPEG video decoder design

The variety of macroblock types and variable-length codes has increased the difficulty in predicting memory accesses and bus utilization pattern for accessing compressed data or pixels to/from external RAMs during the MPEG video decoding process. In this paper, we present a model and a simulator to aid MPEG decoder design by providing useful statistics related to bus utilization and waiting cycles. The model explores MPEG decoder architecture and data nature; it provides results to analyze bus bandwidth and determine proper sizes of decoder I/O buffers connected to the bus. Simulation is performed to test out different bus arbitration schemes for MP@ML data in MPEG-2 decoding.

Mpeg2 Video Encoding in Consumer Electronics

Only very recently, single-chip MPEG2 video encoders are being reported. They are a result of additional interest in encoding in consumer products, apart from broadcast encoding, where a video encoder contains several expensive chips. Only single-chip solutions are cost-effective enough to enable digital recording for the consumer. The professional broadcast encoders are expensive because they use the full MPEG toolkit to guarantee good image quality, at the lowest possible bit-rate. Some MPEG tools are costly in hardware and these are therefore not feasible in single-chip solutions. This results in higher bit-rates, that can be accepted because of the available channel and storage capacity of the latest consumer storage media, harddisk, digital tape (D-VHS) and Digital Versatile Disk (DVD). A consumer product is I.McIC, a single-chip MPEG2 video encoder. It operates in [email protected] mode which can be decoded by all MPEG2 decoders. The IC is highly-integrated, as it contains motion-estimation and compensation, adaptive temporal noise filtering and buffer/bit-rate control. The high-throughput functions of the MPEG algorithm are mapped onto pipelined dedicated hardware, whereas the remaining functions are processed by an application-specific instruction-set processor. Software for this processor can be downloaded, in order to suit the IC for different applications and operating conditions. The IC consists of several communicating processors which were designed using high-level synthesis tools, PHIDEO and DSP Station™.

A common transform engine for MPEG and AC3 audio decoder

A common hardware engine that performs the frequency to time domain transform for both MPEG and Dolby AC3 audio standards is presented. An integral part of the dual mode audio decoder, the cost-effective approach taken here requires minimal computation steps with due consideration of control, address generation, data pipelining, and the overall hardware structure.

Video transport in ATM networks: a systems view

This paper presents a systems view of video transport issues in asynchronous transfer mode (ATM) networks. Since video is a critical component of future distributed multimedia applications, we consider technical approaches necessary to realize a flexible, robust, and efficient ATM framework for video delivery. The overall system-design problem is discussed for a general distributed multimedia computing scenario, and key video-related design issues are identified. This is followed by a more detailed discussion of selected ATM video topics, including: (1) variable bit-rate (VBR) statistical multiplexing and dynamic usage parameter control (VBR+), (2) ATM cell-loss concealment in MPEG decoders, and (3) new transport protocols (“MTP”) for video and multimedia. Supporting simulation or experimental results from ongoing research are given where available.

A practical system for MPEG-2-based video-on-demand over ATM packet networks and the WWW

Abstract A video-on-demand system, dubbed NetMovie, based on MPEG-2 encoded video transmission over ATM networks has been designed and built. It uses a real-time MPEG-2 decoder board on a client personal computer to display compressed video delivered from a remote server over an FDDI/ATM network. Audio play-back is provided using off-the-shelf, digital audio boards. Video compression is done off-line using software encoders. Several transport layer techniques, including dual priority transmission and slice-based packetization, have been developed for error resilient, real-time transmission and audio-video synchronization. The system is integrated with the World Wide Web to provide real-time, high-quality video delivery to end points with high bandwidth connections to the Internet. It demonstrates feasibility of an economical, MPEG-2 video-on-demand system based on readily available hardware and software. NetMovie has been successfully used to demonstrate an MPEG-2 based, international video-on-demand application between NJ, USA and Kyoto, Japan during the 1994 plenipotentiary meeting of the ITU.

Low power design for MPEG-2 video decoder

The I/O power consumption in an MPEG-2 decoder is significant because of the wide connection with large capacitances to the frame buffer. To reduce the power dissipation on the memory bus, the Gray code encoding scheme is proposed to increase the correlation of the image data transferred on the bus. The bit switching probability in the re-coded data will then decrease and in turn the bus power consumption will be reduced. Combined with the proposed bus arbitration and scheduling scheme proposed in this paper, 22% reduction of power dissipation may be achieved.

MPEG decoder architecture for embedded applications

A determinate global data transfer timing scheme will significantly reduce the complexity of global control and ease constraints on sub-modules. Such a scheme allows to construct functional modules based on an explicit performance and data flow requirement. A very low gate count hardware architecture for MPEG decoder is presented to demonstrate the concept.

Set-top box control software: A key component in digital video

The emerging technologies of digital video and high-speed networks are combined together in a set-top box to provide a wide variety of value-added services to consumers. The control software in set-top boxes includes a real-time multi-tasking operating system with extensive multimedia support. Along with digital TV functionality, the control software provides an easy to use functional interface for set-top capabilities, such as MPEG decoding, high-speed broadband network interface, 2-way communications and graphics. An application-level software called the navigator performs basic TV functions and has the ability to download and execute interactive multimedia applications from network servers.

An interactive MPEG-1 browsing system

A personal computer (PC) based interactive MPEG-1 browsing system is proposed. The users can get the general information of MPEG video bitstreams, such as the encoding structure and the header parameters of each encoding layer via this browsing system. The users can also get the detailed information of each decoding step. With the aid of the proposed browsing system, users will have the ability to analyze any MPEG-1 bitstream easily. In addition, this system also provides the capability to encode MPEG-1 video bitstreams and to adjust the encoding parameters interactively when the quality of the encoded video is not good enough. The browsing system can also be a useful tool during the development stage of an MPEG encoding or decoding system.

Architecture of MPEG-2 digital set-top-box for CATV VOD system

We describe an MPEG-2 compliant VOD (video on demand) terminal (e.g. set-top-box) developed for field trial purposes. The hardware architecture of the set-top-box is discussed with emphasis on the graphics system which integrates the MPEG-2 format video, computer graphics and NTSC analog format video. A key point in the implementation of this architecture is the development of a clock rate conversion circuit. The set-top-box contains a one-chip MPEG-2 decoder.

Error Detection and Concealment with an Unsupervised MPEG2 Video Decoder

MPEG2 is an international video coding standard for broad applications ranging from video conferencing to HDTV. In this paper we study the performance of an unsupervised MPEG2 decoder in the presence of bit errors and cell loss, where errors are detected by the decoder solely without requesting any error information from external devices. The technology behind the MPEG2 standard is described briefly. Differences between the MPEG1 and MPEG2 standards are addressed. Schemes to detect errors, based on decoding errors and standard semantics violations, are proposed. Implementation details of the unsupervised MPEG2 decoder are described as necessary to facilitate discussions of these schemes. Computer simulations are conducted for two video sequences with a variety of motions and scene contents to study the visual degradations caused by header information error, random bit error, and cell loss. It is shown that a simple error concealment scheme gives an overall visual quality acceptable to general viewers even under severe transmission error environments.

A PC-based MPEG compressed data decoder

A PC-based MPEG compressed data decoder card is presented. The decoder serves as a PC add-on card and is capable of decoding MPEG compressed data from compact discs (CD) for display on PC monitors. The MPEG decoder is able to accept both MPEG1 audio packets and MPEG1 video packets which conform to the ISO/MPEG1 system and video bitstreams respectively.

Development of an MPEG2 decoder for magneto-optical disk video players

A decoder circuit has been developed which reads out and decompresses high-definition video images recorded on the magneto-optical disk by MPEG2 compression. >

Rate-distortion optimal fast thresholding with complete JPEG/MPEG decoder compatibility

We show a rate-distortion optimal way to threshold or drop the DCT coefficients of the JPEG and MPEG compression standards. Our optimal algorithm uses a fast dynamic programming recursive structure. The primary advantage of our approach lies in its complete compatibility with standard JPEG and MPEG decoders.