MPEG-2 Decoder Research Articles

Сравнение инструментов высокоуровневого синтеза и конструирования цифровой аппаратуры

Application-specific systems with FPGA accelerators are often designed using high-level synthesis or hardware construction tools. Nowadays, there are many frameworks available, both open-source and commercial. In this work, we attempt to fairly compare several existing solutions (languages and tools), including Verilog (our baseline), Chisel, Bluespec SystemVerilog (Bluespec Compiler), DSLX (XLS), MaxJ (MaxCompiler), and C (Bambu and Vivado HLS). Our analysis has been carried out using a representative example of 8×8 inverse discrete cosine transform (IDCT), a widely used algorithm engaged in, among others, JPEG and MPEG decoders. The metrics under consideration include: (a) the degree of automation (how much less code is required compared to Verilog), (b) the controllability (possibility to achieve given design characteristics, namely a given ratio of the performance and area), and (c) the flexibility (ease of design modification to achieve certain characteristics). Rather than focusing on computational kernels only, we have developed AXI-Stream wrappers for the synthesized implementations, which allows adequately evaluating characteristics of the designs when they are used as parts of real computer systems. Our study shows clear examples of what impact specific optimizations (tool settings and source code modifications) have on the overall system performance and area. It emphasizes how important is to be able to control the balance between the communication interface utilization and the computational kernel performance and delivers clear guidelines for the next generation tools for designing FPGA accelerator based systems.

Commutative encryption based video encoding technique with high-efficiency & video adaptation capabilities

Before selecting any algorithm to be used for encryption in multimedia application systems, a thorough analysis of the application must be performed to determine what level of security is required for it to work securely. As a result, after determining the necessary security levels, a careful algorithm selection must be made. The algorithm chosen will have an effect on the speed of the coder-decoder-codec. As a result, it is critical to do so before deciding on an encryption method. The algorithms used in this paper improve the overall efficiency of video encoding scheme and it takes less time comparatively with exiting algorithm approach and experiment result show it take less computation time. Proposed algorithm implemented on MATLAB platform and, performance of the proposed algorithms in order to meet the requirement of real-time MPEG decoding, we have optimized the video frame (I Frame, B Frame) with video adaptation capabilities which provide the facility to run the video in any platform. The proposed algorithms are expected to be widely used in the future to provide security for video-on-demand applications and pay-per-view programs. It can be extended to use it as non-MPEG compression schemes such as H.263 for video-conferencing applications.

Probabilistic Model Checking for Uncertain Scenario-Aware Data Flow

The Scenario-Aware Dataflow (SADF) model is based on concurrent actors that interact via channels. It combines streaming data and control to capture scenarios while incorporating hard and soft real-time aspects. To model data-flow computations that are subject to uncertainty, SADF models are equipped with random primitives. We propose to use probabilistic model checking to analyze uncertain SADF models. We show how measures such as expected time, long-run objectives like throughput, as well as timed reachability—can a given system configuration be reached within a deadline with high probability?—can be automatically determined. The crux of our method is a compositional semantics of SADF with exponential agent execution times combined with automated abstraction techniques akin to partial-order reduction. We present the semantics in detail and show how it accommodates the incorporation of execution platforms, enabling the analysis of energy consumption. The feasibility of our approach is illustrated by analyzing several quantitative measures of an MPEG-4 decoder and an industrial face recognition application.

A low-complexity MPEG-2 to H.264/AVC wavefront intra-frame transcoder architecture

We present a reconfigurable high-throughput MPEG-2 to H.264/AVC intra-frame transcoding architecture with wavefront data processing. The proposed FPGA implementation deals with the highly data-dependent critical path of the transcoder, and with low-complexity synchronization of the encoding and decoding stages. Furthermore, the implementation is applicable for reconfiguration and limits the communication bandwidth to the surrounding system through use of on-chip memory. The computationally demanding units of the MPEG-2 decoder have been implemented by processing 8 pixels in parallel, whereas H.264/AVC encoder engine utilizes a 4 × 4 block-level pipeline. The synchronous communication between the stages and full pipeline of the system is achieved by an intermediate memory buffer mechanism. A wavefront macroblock level scanning order based on the on-the-fly processing of consecutive macroblocks and on-chip memory organization are proposed. Achieved results represent a significant reduction of minimal required frequency compared to the state of the art for resolutions CIF, SD and HD1080p. Furthermore, the proposed transcoding core with encoder stage in full pipeline has maximal throughput of 1744 Mpixels/s that corresponds to processing of UHD 4320p resolution at 30 fps.

Configuration Approaches to Enhance Computing Efficiency of Coarse-Grained Reconfigurable Array

The major bottleneck of coarse-grained reconfigurable arrays (CGRAs) is the excessive configuration overhead; as a result, computing potential cannot be fully utilized. At run-time, the function of CGRAs can be fully and dynamically reconfigured by changing contexts. Therefore, the frequency of context switching on CGRAs is very high. On the other hand, the configuration time of CGRAs is very long. This paper proposes three configuration approaches to reduce interval latency when switching configuration contexts. These proposed approaches include input data relocation (IDR), line-based context switching (LCS), and loop interval minimization (LIM). IDR relocates input data to the first stage of the pipeline; as a result, the delay time for the input data of the next data flow graph (DFG) is reduced. LCS is a LCS mechanism for adjacent independent DFGs to reduce the interval of context switching, thereby expanding the depth of the pipeline. LIM is used to minimize the interval of loops. Simulations on a coarse-grained reconfigurable processor called reconfigurable multimedia system (REMUS) show that 1080 p@30 fps for H.264 high profile video decoding can be achieved under 200 MHz working frequency. As for AVS and MPEG2 decoding algorithms, much higher performance, i.e., 1080 p@39 fps and 1080 p@41 fps, can be achieved respectively.

An MPEG-2 to H.264/AVC intra-frame transcoder architecture with mode decision in transform domain

The computational complexity of the MPEG-2 to H.264/AVC transcoder, in particular the encoder, is technically challenging, but it can be reduced by reusing the information accessible in the decoding process. A low-latency mode decision algorithm performed in transform domain within the MPEG-2 decoder is proposed. The encoder stage contains two mutually exclusive intra prediction algorithms of block sizes 4x4 and 16x16 sharing the hardware logic. The shared intra prediction unit is supported by an on-chip memory organization. The proposed architecture is implemented on FPGA development board. Its implementation supports high throughputs that correspond to a real-time processing of a variety of video resolutions including QFHD 2160p at 30 fps. Furthermore, the minimal required frequency for CIF, SD and HD1080p resolutions are significantly reduced compared to the state of the art1.

LCD TV의 핵심기술 선정방법에 관한 연구

One of the most important decision making is which product's components should make in-house and which should they outsource. This paper suggests a framework to solve above question. This paper applies to LCD TV industry with AHP analysis. The results shows that Scaler chip, LCD panel, MPEG decoder, and Video decoder are important components. Samsung Electronics turn out make in-house these core component. This research will be a good guideline for selecting core component.

Parallelizing MPEG Decoder with Scalable Streaming Computation Kernels

In this paper, we describe a scalable and portable parallelized implementation of a MPEG decoder using a streaming computation paradigm, tailored to new generations of multi—core systems. A novel, hybrid approach towards parallelization of both new and legacy applications is described, where only data—intensive and performance—critical parts are implemented in the streaming domain. An architecture—independent StreamIt language is used for design, optimization and implementation of parallelized segments, while the developed StreamGate interface provides a communication mechanism between the implementation domains. The proposed hybrid approach was employed in re—factoring of a reference MPEG video decoder implementation; identifying the most performance—critical segments and re—implementing them in StreamIt language, with StreamGate interface as a communication mechanism between the host and streaming kernel. We evaluated the scalability of the decoder with respect to the number of cores, video frame formats, sizes and decomposition. Decoder performance was examined in the presence of different processor load configurations and with respect to the number of simultaneously processed frames.

Multi-objective exploitation of pipeline parallelism using clustering, replication and duplication in embedded multi-core systems

With the popularity of mobile device, people require more computing power to run emerging applications. However, the increase in power consumption is a major problem because power is quite limited in embedded systems. Our goal is to consider power consumption along with latency and throughput. We proposed a heuristic algorithm, called Parallel Pipeline Latency Optimization for high performance embedded systems (PaPiLO), based on clustering, replication and duplication, to minimize latency under power and throughput constraints. Experimental results show our method can get 15% latency reduction and 10% improvements for random task graphs and MPEG-2 decoder, respectively.

A Prototype-Based Gate-Level Cycle-Accurate Methodology for SoC Performance Exploration and Estimation

A prototype-based SoC performance estimation methodology was proposed for consumer electronics design. Traditionally, prototypes are usually used in system verification before SoC tapeout, which is without accurate SoC performance exploration and estimation. This paper attempted to carefully model the SoC prototype as a performance estimator and explore the environment of SoC performance. The prototype met the gate-level cycle-accurate requirement, which covered the effect of embedded processor, on-chip bus structure, IP design, embedded OS, GUI systems, and application programs. The prototype configuration, chip post-layout simulation result, and the measured parameters of SoC prototypes were merged to model a target SoC design. The system performance was examined according to the proposed estimation models, the profiling result of the application programs ported on prototypes, and the timing parameters from the post-layout simulation of the target SoC. The experimental result showed that the proposed method was accompanied with only an average of 2.08% of error for an MPEG-4 decoder SoC at simple profile level 2 specifications.

Accelerating throughput-aware runtime mapping for heterogeneous MPSoCs

Modern embedded systems need to support multiple time-constrained multimedia applications that often employ multiprocessor-systems-on-chip (MPSoCs). Such systems need to be optimized for resource usage and energy consumption. It is well understood that a design-time approach cannot provide timing guarantees for all the applications due to its inability to cater for dynamism in applications. However, a runtime approach consumes large computation requirements at runtime and hence may not lend well to constrained-aware mapping. In this article, we present a hybrid approach for efficient mapping of applications in such systems. For each application to be supported in the system, the approach performs extensive design-space exploration (DSE) at design time to derive multiple design points representing throughput and energy consumption at different resource combinations. One of these points is selected at runtime efficiently, depending upon the desired throughput while optimizing for energy consumption and resource usage. While most of the existing DSE strategies consider a fixed multiprocessor platform architecture, our DSE considers a generic architecture, making DSE results applicable to any target platform. All the compute-intensive analysis is performed during DSE, which leaves for minimum computation at runtime. The approach is capable of handling dynamism in applications by considering their runtime aspects and providing timing guarantees. The presented approach is used to carry out a DSE case study for models of real-life multimedia applications: H.263 decoder, H.263 encoder, MPEG-4 decoder, JPEG decoder, sample rate converter, and MP3 decoder. At runtime, the design points are used to map the applications on a heterogeneous MPSoC. Experimental results reveal that the proposed approach provides faster DSE, better design points, and efficient runtime mapping when compared to other approaches. In particular, we show that DSE is faster by 83% and runtime mapping is accelerated by 93% for some cases. Further, we study the scalability of the approach by considering applications with large numbers of tasks.

Improving QoE in multicast IPTV systems: Channel zapping times

The usage of Internet Protocol TV (IPTV) deployments in the consumer electronics market is growing very popular in recent years. In IPTV multicast systems, quality of experience is a very critical factor for user satisfaction. Existing and future IPTV systems will offer a large number of channels to users. The most important factors that affect the quality of experience in IPTV systems are channel zapping times. Generally, the channel zapping time depends on several parameters like IGMP command process time, network delay time, IPTV consumer device processing delay time, jitter buffer delay time, MPEG decoder time and conditional access/digital rights management (CA/DRM) delay time. In this paper, we presented an analysis of channel zapping time in IPTV systems and we proposed a new approach based on channel-based peer selection, called CBPS where the peer partner to construct peer-to-peer communication is discovered and unicast stream for joined channel will be get from peer partner during zapping process. By this way, black screen will not be displayed to user during zapping process until the channel stream coming from server is available. The simulation results in OPNET Modeler have been provided to demonstrate the performance of the proposed algorithm. Key words: Internet protocol TV, channel zapping times, peer-to-peer transmission, quality of experience.

System-level design optimization of reliable and low power multiprocessor system-on-chip

In this paper, we study the impact of application task mapping on the reliability of multiprocessor system-on-chip (MPSoC) application in the presence of soft errors. Based on this study, we propose a novel system-level design optimization of an MPSoC application through joint power minimization and reliability improvement. The power minimization is carried out using voltage scaling technique, while reliability improvement is achieved through careful choice of application task mapping on the homogeneous MPSoC processing cores. The overall aim is to minimize the number of single-event upsets (SEUs) experienced by the MPSoC application for suitably identified voltage scaling of the system processing cores such that the power is reduced and the specified real-time constraint is met. We evaluate the effectiveness of the proposed design optimization using a number of different applications, including MPEG-2 video decoder and synthetic applications. We show that for an MPEG-2 decoder with four processing cores, the proposed soft error-aware optimization produces a design with 38% less SEUs than soft error-unaware design optimization for an arbitrary soft error rate of 10−9, while consuming 9% less power and meeting a given real-time constraint. Furthermore, we investigate the impact of architecture allocation (allocation of processing cores) and show that for an MPSoC with six processing cores and a given real-time constraint, the proposed optimization produces design with up to 7% less SEUs compared to soft error-unaware designs at the cost of 5.5% higher power.

Provably Secure Active IC Metering Techniques for Piracy Avoidance and Digital Rights Management

In the horizontal semiconductor business model where the designer's intellectual property (IP) is transparent to foundry and to other entities on the production chain, integrated circuits (ICs) overbuilding and IP piracy are prevalent problems. Active metering is a suite of methods enabling the designers to control their chips postfabrication. We provide a comprehensive description of the first known active hardware metering method and introduce new formal security proofs. The active metering method uniquely and automatically locks each IC upon manufacturing, such that the IP rights owner is the only entity that can provide the specific key to unlock or otherwise control each chip. The IC control mechanism exploits: 1) the functional description of the design, and 2) unique and unclonable IC identifiers. The locks are embedded by modifying the structure of the hardware computation model, in the form of a finite state machine (FSM). We show that for each IC hiding the locking states within the modified FSM structure can be constructed as an instance of a general output multipoint function that can be provably efficiently obfuscated. The hidden locks within the FSM may also be used for remote enabling and disabling of chips by the IP rights owner during the IC's normal operation. An automatic synthesis method for low overhead hardware implementation is devised. Attacks and countermeasures are addressed. Experimental evaluations demonstrate the low overhead of the method. Proof-of-concept implementation on the H.264 MPEG decoder automatically synthesized on a Xilinix Virtex-5 field-programmable gate array (FPGA) further shows the practicality, security, and the low overhead of the new method.

Audio signal processing adapted to mobile reception of DVB-T

Mobile reception of digital TV (DTV) is becoming popular and signal processing has to be adapted to the new requirements. This is already done for the DTV receivers but the MPEG decoders are still subject to improvement. Since audio errors are perceived as being much more annoying than video errors, this paper focuses on the adaptations of the audio signal processing. An evaluation of the influence of mobile transmission errors on the audio processing is presented and adaptations are proposed. We show that the amount of correctly decoded frames can be increased by up to 5 % whereas the amount of incorrectly decoded frames can be decreased by up to 16 %. Both will result in an improvement of the perceived audio quality <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1</sup> .

Embedded Real-Time MPEG-4 Decoder Based on ADSP-BF527

In this paper, we propose an embedded real-time MPEG-4 decoder based on ADSP-BF527 Blackfin DSP. In order to achieve the real-time requirement of MPEG-4 decoding, we modify and optimize the decoding modules. Firstly, we analyze the number of operations for various modules, and then use two buffer groups (BG) as parallel decoding mechanism of broadcast transformation. Finally, we make use of direct memory access (DMA) to carry out program steps. Experimental results demonstrate that the proposed method can decode a CIF video which reduces approximately 40.3 MHz core cycles. In addition, the decoded frame playing rate can increase from 3 fps to 25 fps when applied the PPI procedure. The playing rate can reach above 30 fps as using QCIF video so that the proposed method can achieve a real-time decoder and player.

A Fast Mode Decision Algorithm from MPEG-2 to H.264 Transcoding

In order to reduce the complexity of MPEG-2 to H.264 transcoding, an efficient fast mode decision algorithm is proposed. We apply machine learning principles by building a decision tree (the relationship between the information gathered during the MPEG-2 decoding stage and the H.264 coding modes of MBs) enabling the development of very low complexity transcoding mechanism. The decision tree is used to determine the coding modes of the P-frames MBs of the output H.264 encoded video sequences. Experimental results show that the proposed algorithm can dramatically reduce the transcoding time, with high quality and high coding efficiency of image.

LLVM-based and scalable MPEG-RVC decoder

MPEG reconfigurable video coding (RVC) is a new platform-independent specification methodology chosen by the MPEG community for describing coding standards. This methodology aims at producing abstract decoder models (ADMs) of MPEG decoders as programs described in a dataflow language namely Actor Language (RVC-CAL). RVC-CAL naturally expresses potential parallelism between tasks of an application, which makes an ADM description suitable for implementation to a wide variety of platforms, from uniprocessor systems to FPGAs. MPEG RVC eases the development process of decoders by building decoders at a library-component level instead of using monolithic algorithms, and by providing a library of coding tools standardized in MPEG. This paper presents new mechanisms based on the low level virtual machine that allow the conception of a decoder able to dynamically instantiate several RVC decoder descriptions. This decoder, unlike static decoders generated by RVC tools, keeps de facto the features of an RVC description namely portability, scalability and reconfigurability.

Improving cache locking performance of modern embedded systems via the addition of a miss table at the L2 cache level

To confer the robustness and high quality of service, modern computing architectures running real-time applications should provide high system performance and high timing predictability. Cache memory is used to improve performance by bridging the speed gap between the main memory and CPU. However, the cache introduces timing unpredictability creating serious challenges for real-time applications. Herein, we introduce a miss table (MT) based cache locking scheme at level-2 (L2) cache to further improve the timing predictability and system performance/power ratio. The MT holds information of block addresses related to the application being processed which cause most cache misses if not locked. Information in MT is used for efficient selection of the blocks to be locked and victim blocks to be replaced. This MT based approach improves timing predictability by locking important blocks with the highest number of misses inside the cache for the entire execution time. In addition, this technique decreases the average delay per task and total power consumption by reducing cache misses and avoiding unnecessary data transfers. This MT based solution is effective for both uniprocessors and multicores. We evaluate the proposed MT-based cache locking scheme by simulating an 8-core processor with 2 levels of caches using MPEG4 decoding, H.264/AVC decoding, FFT, and MI workloads. Experimental results show that in addition to improving the predictability, a reduction of 21% in mean delay per task and a reduction of 18% in total power consumption are achieved for MPEG4 (and H.264/AVC) by using MT and locking 25% of the L2. The MT results in about 5% delay and power reductions on these video applications, possibly more on applications with worse cache behavior. For the FFT and MI (and other) applications whose code fits inside the level-1 instruction (I1) cache, the mean delay per task increases only by 3% and total power consumption increases by 2% due to the addition of the MT.

Development of Digital Watermark Inserting and Detecting System for MPEG-2 Codec

This paper describes a study on developing an insert and detect system of digital watermark to the MPEG-2 coder and decoder. Digital watermark inserting system substitutes a coefficient among the DCT coefficients for new one. This replacement performs in MPEG-2 PS format. Watermark detecting system analyzes the input data stream of MPEG-2 and detect the probability of occurrence of a specific code or watermarking code. Our inserting system had very high invisibility and the PSNR of the results was 130 dB around. And our detection rate of watermark was over 99% in digital format and over 85% in analog captured format according to the quality of contents.