MPEG-1 Audio Layer Research Articles

A warped linear-prediction-based subband audio coding algorithm

A novel audio coding algorithm is proposed where the warped-linear prediction (WLP) technique is employed to construct a perceptual pre- and post-filter for subband audio coding. A modified signal-to-mask ratio (SMR) calculation is given for subband coding of the WLP residuals of audio signals. The concept of perceptual entropy (PE) is extended to subband coding, resulting in the subband perceptual entropy (SPE), which gives a short time estimate of the lowest possible bit rate for transparent subband audio coding. Two WLP models with frequency responses approximating the spectral shape of the masking threshold are investigated and it is found that the residual signals of both models contain less SPE compared with that of the original audio signals. Subjective tests show that the proposed audio codec operating at 56 kbps has a perceptual quality comparable to MPEG-1 audio Layer II operating at 64 kbps.

A fixed-point MPEG audio processor operating at low frequency

A fixed-point pipelined processor optimized for decoding MPEG-1 audio layer III (MP3) is presented. Various examination and experiments on the decoding algorithm are exploited to lower the operating frequency by providing efficient instructions and addressing modes, because low frequency is directly related to low power consumption. Accordingly, the dynamic scaling method is used to preserve the precision while computing in fixed-point arithmetic. Also, a novel instruction set tuned for MP3 decoding is presented. The resulting cycle count required to decode a frame is so small that the proposed processor can operate with 12.8 MHz while decoding in real-time.

A low power full accuracy MPEG1 audio layer III (MP3) decoder with on-chip data converters

A low power full accuracy MPEG1 audio layer 3 (MP3) decoder with on-chip A/D converter (ADC) and D/A converter (DAC) is proposed. The chip is composed of a digital block to implement the MP3 decoding algorithm and voice compression/decompression algorithm, a 12-bit recycling type ADC, and an oversampling /spl Delta//spl Sigma/ 1-bit DAC. In order to satisfy the full accuracy specification of the MP3 decoder, a novel 32-bit floating DSP core is proposed. Further, an efficient power management technique is implemented to reduce power consumption for portable applications. The proposed decoder has been fabricated with a 4 metal 0.35 /spl mu/m CMOS technology and the chip area is about 6.4/spl times/6.7 mm/sup 2/ with 165 mW power dissipation at 2.7 V power supply.