Types Of MOSFETs Research Articles

Direct Single Impinging Jet Cooling of a <sc>mosfet</sc> Power Electronic Module

This paper presents an approach of direct liquid jet impingement cooling of a typical mosfet power module. A single micro water jet was installed for cooling the upper surface of a mosfet semiconductor package. In contrast to standard cooling methods, this approach focuses on hot spot removal omitting any kind of heat spreading device. The cooling chamber was directly soldered to the mosfet cover that represents a very efficient way of liquid cooling. Two different configurations with and without electrical insulation (TIM) were used to investigate the importance of insulating material. In the range of 10–100 mL/min coolant flow rates at an inlet temperature of 22.5 $^\circ$ C a maximum power distribution of 51 W (at 30 mL/min) next to a maximum measured mosfet temperature of 163 $^\circ$ C could be realized. Heat transfer coefficients up to 12 000 W/m $^{2}\cdot$ K were achieved using only 10.8 cm $^{3}$ of assembly space for the cooling device. With electrical insulation, the heat transfer coefficient exceeded 6000 W/m $^{2}\cdot$ K at a coolant flow rate of 30 mL/min and pumping power of 3 mW. The results illustrate the potential of direct liquid cooling using impinging microjets in combination with a compact injection chamber. The individual cooling of semiconductors offers new perspectives in the design of power electronic modules.

Experimental Investigations of State-of-the-Art 650-V Class Power MOSFETs for Cryogenic Power Conversion at 77K

With consideration of both the operating properties from cryogenic MOSFETs and refrigerating costs from cryogenic refrigerators, this paper attempts to carry out the experimental tests and performance evaluations of state-of-the-art 650-V class MOSFETs, and thus to explore a possible design guideline for cryogenic power conversions at liquid nitrogen temperature. Three cryogenic operating behaviors of on-state resistances and breakdown voltages of five types of commercial power MOSFETs and on-state voltage across their built-in reverse diodes are tested from 300 K to 77 K. The measured on-state resistances obtained in low-current tests show almost double-exponential functional relations with the operating temperatures, while the other two cryogenic parameters are directly or inversely proportional to the operating temperatures. Moreover, cryogenic on-state resistance behaviors in high-current tests from 20 A to 90 A are also found to have double-exponential functional relations with the operating currents. Based on the experimental results and their fitted temperature-dependent and current-dependent functions, integrated evaluation of overall energy efficiency involved with refrigerating cost is presented to form a feasible design guideline for cryogenic power conversions. Finally, two 40-kW and 4-MW boost choppers are conceptually designed and discussed to verify the proposed design guideline for the use in various MOSFET-based cryogenic power conversions.

(Invited) Interface Defects in C-face 4H-SiC MOSFETs: An Electrically-Detected-Magnetic-Resonance Study

Silicon carbide metal-oxide-semiconductor field-effect transistors (SiC-MOSFETs) are promising for next-generation power transistors. In general, SiC-MOSFETs are fabricated using a 4H-SiC(0001) (“Si face”) surface to ensure the stability in their threshold voltages (V th). In contrast, a 4H-SiC(000-1) (“C face”) surface exhibits a wider range of the V th instability, although C-face MOSFETs can achieve a much higher field-effect mobility (μ = 60-100 cm2/V·s) than the standard Si-face MOSFETs (μ = 20-30 cm2/V·s) [1]. If the C-face MOSFETs overcome their V th instability, they become excellent high-performance SiC-MOSFETs. Furthermore, since the C face resemble to other high-μ surfaces such as “m face” and “a face,” understanding of the C-face MOS interfaces will be useful for the other important interfaces. The development of a number of C-face MOSFETs has revealed that there are opposite types of C-face MOSFETs with quite different V th instabilities [2]. We classified them into “good type” and “bad type,” depending on their V th instabilities. The “bad-type” MOSFETs commonly showed a large V th shift; the drain-current (I d) versus gate-voltage (V g) curve was horizontally shifted toward the negative direction after applying a negative V g stress (-30 V) for 103 sec. On the contrary, in the “good-type” MOSFETs, the negative V th shift is drastically reduced even against a much longer stress time (104 sec). Curiously, the same epi-wafer or the same oxidation process caused both the types of C-face MOSFETs [2]. Therefore, from a view point of fabrication processes, it was difficult to understand the cause of the V th instability. To clarify a microscopic mechanism of the V th instability, we performed an electrically-detected-magnetic-resonance (EDMR) study on interface defects related to the V thinstability of C-face MOSFETs. EDMR enables us to detect electron-spin-resonance (ESR) centers in small-sized electronic devices [1]. We prepared lateral n-channel C-face 4H-SiC MOSFETs on 4º-off 4H-SiC(000-1) epi-wafers. A 50-nm-thick gate oxide was grown by wet oxidation at 1000ºC and was subjected to H2 POA at 1100ºC for 30 min. This process ensured a high μ over 60 cm2/V·s. Some of the MOSFETs were subjected to gamma-ray irradiation in order to de-passivate hydrogen-terminated interface states. After the irradiation, we observed an increase in the V thshift [2]. The dose was set to 0.5 to 40 Mrad. EDMR measurements were carried out at room temperature with a 1.5-kHz magnetic-field modulation. EDMR spectra of both the “bad-type” and “good-type” MOSFETs were dominated by the same defect, that we named “C-face defects” [1,2]. A primary difference among the two types was found in their signal intensities; i.e., the “bad-type” samples revealed much larger EDMR signal intensities than the “good-type” ones. The C-face defects were only detectable under a negative V g, indicating that they have doubly-occupied levels (ESR-inactive states) in V g ≥ 0V. Furthermore, we assigned these levels to be neutral donor levels, because they should be electrically-inactive in V g ≥ 0V. EDMR signal intensities increased with increasing a negative V g, due to a conversion from doubly-occupied states (ESR-inactive, charge = 0) to singly-occupied states (ESR-active, charge = +1). Further increasing a negative V g, the signal intensity reached a peak at a certain V g (we define it as V peak) and turned into a decrease. This behavior indicates that the formation of empty states (ESR-inactive, charge = +2) has started. From the V g dependence, we can estimate the density of the C-face defects (N levels), because V peak should be dependent on N levels. We performed device simulations on our C-face MOSFETs to estimate a relationship between V peak and N levels. Finally, N levels of various C-face MOSFETs were estimated over a wide range from 4×1012 cm-2 to 13×1012 cm-2. We also found that N levels strongly correlated with the negative V th shifts in the C-face MOSFETs, meaning that the C-face defects are related to the negative V th shifts or positive fixed charges in the oxide layer. However, EDMR did not focus on the oxide layer. After removing a negative V g, the EDMR signals disappeared immediately, clearly indicating that EDMR observed hole traps at the interface. The strong correlation between interfacial hole traps (C-face defects) and the positive fixed charges (hole traps in the oxide layer) suggests that the C-face defects are also formed in the oxide layer. They may be partly incorporated into the oxide layer during the oxidation. By reducing the C-face defects as small as possible, we can obtain high-performance SiC-MOSFETs with both high channel mobility and high reliability in V th. [1] T. Umeda et al., ECS Transactions vol. 58, 7 (2013). [2] G. W. Kim et al., Mater. Sci. Forum vol. 858, 591 (2016).

Charge based, continuous compact model for the channel current in organic thin-film transistors for all regions of operation

In general most modeling approaches for organic field-effect transistors (OFETs) are based on the typical MOSFET equations. The threshold voltage is usually a fitting parameter without relation to physical parameters hence the impact of their variability on the threshold voltage is not clear. The presented modeling approach is charge based with a continuous equation for the channel current in organic field-effect transistors from below to above threshold. The model provides a physics based parameter set related to trap states, and a compatible parameter set from a circuit designer’s perspective. An expression for the threshold voltage is derived depending on the density of trap states. The model considers a power-law mobility model, parasitic contact resistances and channel length modulation effects and is verified with measurements on OFETs fabricated with small molecules.

50-nm Nano-Scaled Vertical-Transistor with NiSi₂ Seed-Induced Vertically Crystallized Poly-Silicon Channel for Very-Large-Scale-Integration.

Vertical-channel MOSFETs are hard to demonstrate a high electrical performance than the planar MOSFETs because of its polycrystalline-silicon (poly-Si) channel for 3-D CMOS ICs. In this paper, we have demonstrated a vertical poly-silicon-channel (VPSC) transistor NiSi2 seed-induced vertical crystallization (SIVC) and compared with the typical SG-VPC MOSFETs with solid-phase crystallization (SPC). The SIVC poly-Si showed large longitudinal grains with low defect trap sites, while the SPC poly-Si showed small spherical grains with large defect trap sites. Therefore, the electrical performance of SG-VPC MOSFETs with SIVC was superior to the SG-VPC MOSFETs with SPC in all aspects.

First principles investigation of SiC/AlGaN(0001) band offset

We are attempting to develop a new type of vertical MOSFET with SiC/AlGaN heterojunction. Toward the realization of the vertical MOSFET, the control of conduction-band offset is one of the crucial subjects. We investigated the conduction-band offset of 4H-SiC/AlxGa1-xN interface by the first-principles electronic structure calculations. We found that the offset of the interface with 40% Al content becomes almost zero. Therefore, 4H-SiC/Al0.4Ga0.6N interface is one of the most promising candidates for the vertical MOSFET in future power conversion devices.

On the Design Process of a 6-kVA Quasi-Z-inverter Employing SiC Power Devices

This paper presents the design process of a 6-kVA quasi-Z-source inverter built with SiC power devices, in particular, employing SiC MOSFETs and SiC Schottky diodes. The main design target is to find the optimal parameters and a good agreement between the efficiency and power density of the converter. The performance of the system may be influenced not only by the switching frequency but also from the specific pulsewidth modulated (PWM) method or type of SiC MOSFET, and, therefore, various design cases are analyzed. At a final step, the 6 kVA/3 × 400 VAC inverter employing the 80 mΩ SiC MOSFETs and operating at 100 kHz with the minimum switching number method is chosen for investigation and a laboratory prototype is built. From experiments, the high performance of the designed system is confirmed. More specifically, it is shown that an efficiency above 95.6% (at 400 VDC, B = 1.9) and a power density higher than 2 kW/dm3 have been reached. Last but not least, the obtained results, which can be recognized as leading in the area of impedance source converters, show the great benefits gained by employing the new power semiconductor devices.

P.2.e.006 - Antidepressant-like properties of the GPR39 (zinc receptor) agonist

To present results of irradiation of ophthalmopathy in the course of Graves-Basedow disease performed in the Radiotherapy Laboratory in University Children's Hospital in Cracow by staff of the Oncology Clinic, Collegium Medicum Jagiellonian University (CM UJ).During the period of 2000–2003 therapeutic irradiation of the retrobulbar area was performed in 121 patients with malignant exophthalmos using a total dose of 20 Gy/ 10 fractions of 6 MV photonic beam in the Radiotherapy Laboratory in University Children's Hospital in Cracow. Execution of the treatment plan was controlled by in vivo dose measurements using semiconducting detectors, MOSFET type. Radiotherapy was preceded by intravenous corticosteroid therapy (Solu Medrol) with a dose of 2g/ week for 4 weeks.During the irradiation treatment 9 patients (7.4%) developed an acute post-radiation reaction of transient character. Ophthalmological control examination revealed an improvement in 97 patients (80.2%) in the form of reduction or total regression of ophthalmopathy symptoms; in 21 other patients (17.3%) stabilization was noted and progression in 3 (2.5%).Radiotherapy is a well-tolerated method of ophthalmopathy treatment in the cour se of Graves-Basedow disease. Efficacy of radiotherapy as an exclusive method of malignant exophthalmos treatment seems to be lower in comparison to irradiation combined with corticosteroid therapy.

Experimental Study on Deformation Potential (<inline-formula> <tex-math notation="LaTeX">${D}_{{{ac}}}$ </tex-math> </inline-formula>) in MOSFETs: Demonstration of Increased <inline-formula> <tex-math notation="LaTeX">${D}_{{{ac}}}$ </tex-math> </inline-formula> at MOS Interfaces and Its Impact on Electron Mobility

Deformation potential ( $D_{ac}$ ), which is one of the most important parameters determining the rate of electron–acoustic phonon scattering, in Si around MOS interfaces is thoroughly studied with regard to the dependences on surface carrier densities, back-gate biases, and device structures. It is demonstrated that $D_{ac}$ increases sharply at the MOS interface. To investigate the impact of the increased $D_{ac}$ on $\mu _{e}$ , thick body-channel SOI MOSFETs, where drain current flows in the entire SOI layers, was fabricated. The carrier transport experiments reveal that $\mu _{e}$ of greater than 1100 cm $^{2}\text{V}^{-1}\text{s}^{-1}$ is obtained in body-channel SOI MOSFETs with the SOI thickness of greater than 70 nm. By taking into account the $D_{ac}$ profile around the MOS interface, experimental $\mu _{e}$ of SOI MOSFETs is numerically reproduced over a wide range of SOI thicknesses. $\mu _{e}$ of the body-channel SOI MOSFETs is also well reproduced using the same $D_{ac}$ profile. Thus, it is concluded that $D_{ac}$ increases sharply at the Si/SiO2 interface. The accurate modeling of the increased $D_{ac}$ around the Si/SiO2 interface is indispensable for designing high-performance and/or low-power 3-D MOSFETs including FinFETs, extremely thin SOI MOSFETs, and nanowire MOSFETs, because these types of MOSFETs have greater interface-to-volume ratios.

Characterization and Comparison of Planar and Trench Silicon Carbide (SiC) Power MOSFETs

This paper presents a comprehensive evaluation and experimental comparison of silicon carbide power MOSFETs through double pulse test. First, a universal hardware platform is designed and developed to test power semiconductor devices with various device packages and measuring requirements. Using the developed platform, the static characteristics and switching performance of the two types of SiC MOSFETs (one planar and one trench type) are evaluated under different case temperatures from 25 oC to 175 oC. Based on the evaluation data, a comparison of both SiC MOSFETs is conducted in terms of their on-state resistance, switching loss, and temperature dependent behavior. It is found that the latest trench SiC MOSFETs present similar switching loss while much lower conduction loss compared to existing commercial planar SiC MOSFETs. Moreover, the trench devices show a nearly temperature independent switching loss, which is beneficial to suppress the potential thermal runaway issue under high temperature continuous operation.

(Invited) Silicon Emission Mechanism for Oxidation Process of Non-Planar Silicon

Recent aggressive progress of the device technology demands development of three-dimensional non-planar channel MOSFETs. The oxidation process of non-planar silicon is one of the most important keys. Silicon oxidation is the fundamental but very important process for fabricating the gate dielectrics/silicon interface, which governs the performance of MOSFETs. Historically it had been believed that this process consists of only two elementary processes, the oxygen diffusion through the oxide and the oxygen reaction at the interface between the oxide and the silicon as explained by Deal and Grove in 1965. Afterwards, it has been revealed that this process also consists of the additional process of silicon emission from the interface into the oxide. Our theoretical studies combining the first-principles calculation approach with the rate-diffusion equation approach clearly showed that the inclusion of the silicon emission process can consistently explain the unaccounted initial enhanced oxidation. The theory can also naturally explain the oxidant pressure dependence and the substrate orientation dependence of the oxide growth kinetics. In addition, the experimental study with HRBS clearly detected silicon atoms diffused from the interface through the oxide after the thermal oxidation. Therefore, the silicon emission mechanism is inevitable for the atomic-level control of the gate-dielectrics-fabrication process. Even if the surface is covered with high-k dielectric films, thermal treatments promote silicon diffusion through the films towards the surface because the oxygen atoms in the films naturally react with the silicon at the interface. The silicon emission also causes interfacial defects, which become the charge traps. The emission further causes density fluctuation of the grown oxide, which leads to the leakage current paths for the stress-induced dielectric break down. The emission thus plays important roles for the performance of gate dielectrics. The situation could not be changed even when the channels of MOSFETs becomes non-planar from planar. For the typical non-planar MOSFET such as the vertical BC-MOSFET, the channel has the shape of a pillar. The experiment on the oxidation of the silicon pillar reported unaccounted missing silicon. 50% in maximum of silicon atoms in the initial pillar disappear after the thermal oxidation. This phenomenon can also be explained by the silicon emission mechanism if almost all of the silicon atoms diffused through the oxide evaporate from the oxide surface as SiO gas. Because the area of the interface is smaller than that of the oxide surface, the interface density of the emitted silicon is geometrically larger than the surface density. Therefore, the silicon diffusion through the oxide is enhanced more than that in the planar case. This means that the missing silicon is inevitable for the oxidation process of non-planar channels. Careful fabrication approaches are necessary to achieve high-performance non-planar MOSFETs. This work has been supported by a grant from "Three-Dimensional Integrated Circuits Technology Based on Vertical BC-MOSFET and Its Advanced Application Exploration" of ACCEL under JST.

Characterization and Comparison of Planar and Trench Silicon Carbide (SiC) Power MOSFETs

This paper presents a comprehensive evaluation and experimental comparison of silicon carbide power MOSFETs through double pulse test. First, a universal hardware platform is designed and developed to test power semiconductor devices with various device packages and measuring requirements. Using the developed platform, the static characteristics and switching performance of the two types of SiC MOSFETs (one planar and one trench type) are evaluated under different case temperatures from 25 oC to 175 oC. Based on the evaluation data, a comparison of both SiC MOSFETs is conducted in terms of their on-state resistance, switching loss, and temperature dependent behavior. It is found that the latest trench SiC MOSFETs present similar switching loss while much lower conduction loss compared to existing commercial planar SiC MOSFETs. Moreover, the trench devices show a nearly temperature independent switching loss, which is beneficial to suppress the potential thermal runaway issue under high temperature continuous operation.

A Typical MOSFET Modeling Procedure for RF Analog Circuit Design

This paper presents a theoretical yet practical device targeting method to extract typical model parameters of MOSFET devices on wafer for RF analog integrated circuit design. This method employs skewing algorithms with model parameters of existing typical device which are selected by using inter-lot process electrical test parameters. Although this technique can be applied for both n-channel and p-channel MOSFETs, only n-channel devices could be prepared for our experiments in this research. To demonstrate the plausibility of this method, a cascode amplifier is designed to simulate frequency characteristic of S21 with this method.

Impact of Surface Passivation on the Dynamic ON-Resistance of Proton-Irradiated AlGaN/GaN HEMTs

Radiation tolerance of AlGaN/GaN high-electron mobility transistors (HEMTs) is studied with 2-MeV protons, up to a fluence of $6 \times 10^{14}$ H+/cm2 (about 200 times of typical Si MOSFET rating). The increase in dynamic ON-resistance ( $R_{{\textit{ONDYN}}})$ after radiation is observed to be much more severe than that of static ON-resistance. Radiation-induced donorlike traps located near the two-dimensional electron gas trap electrons, which is responsible for the phenomenon. Compared with the devices passivated by conventional plasma-enhanced chemical vapor deposition (PECVD) SiN, GaN HEMTs with 10 nm of in situ SiN before the PECVD SiN step demonstrate much less increase in $R_{{\textit{ONDYN}}}$ from 2300% to only 300%. The in situ SiN is believed to reduce the process damage by PECVD, improving radiation tolerance.

Temperature-Dependent Short-Circuit Capability of Silicon Carbide Power MOSFETs

This paper presents a comprehensive short-circuit ruggedness evaluation and numerical investigation of up-to-date commercial silicon carbide (SiC) MOSFETs. The short-circuit capability of three types of commercial 1200-V SiC MOSFETs is tested under various conditions, with case temperatures from 25 to 200 °C and dc bus voltages from 400 to 750 V. It is found that the commercial SiC MOSFETs can withstand short-circuit current for only several microseconds with a dc bus voltage of 750 V and case temperature of 200 °C. The experimental short-circuit behaviors are compared, and analyzed through numerical thermal dynamic simulation. Specifically, an electrothermal model is built to estimate the device internal temperature distribution, considering the temperature-dependent thermal properties of SiC material. Based on the temperature information, a leakage current model is derived to calculate the main leakage current components (i.e., thermal, diffusion, and avalanche generation currents). Numerical results show that the short-circuit failure mechanisms of SiC MOSFETs can be thermal generation current induced thermal runaway or high-temperature-related gate oxide damage.

(Invited) Charge-Based Modelling of the Channel Current in Organic Field Effect Transistors Considering Injection Effects

Models for the current calculation in organic field-effect transistors (OFETs) are usually based on the typical MOSFET equations. Two different independent equations connected by the threshold voltage are used, in which the threshold voltage is usually a fitting parameter without relation to physical parameters hence the impact of their variability on the threshold voltage is not clear. We present a modeling approach for the device current in OFETs which is physically- and charge-based with a continuous equation for the channel current in organic field-effect transistors. It is assumed that the conducting channel of an OFET is reduced to a small number of monolayers of a specific thickness dm where the accumulated charge is uniformly distributed [1] as well as that all traps are filled in the on-state of the device (trapped charges qNt). The accumulated mobile charge per area Q’m is calculated and is a function of that specific thickness dm, the density of shallow traps Nc, and the surface potential ΦC. While calculating the mobile charge Q’m via the Poisson’s equation it gets obviously that there is no closed form solution for the surface potential ΦC. So it is solved once numerically for a given voltage VGS=V0 and kept constant for a given technology. The value of that (arbitrarily) chosen voltage within the operating regime and the corresponding mobile charge Q’m0 have almost no influence on the final result of the current and the threshold voltage. Closed form solutions for mobile charges at the source/drain end of the channel have been derived [2] and are used for the calculation of the channel current IDS/channel considering a diffusion and a drift part of the current. In the presented approach the mobile charges densities are a function of VGS, Q’m0, and V0. An expression of the threshold voltage Vthis also found. The injection effects occurring at the metal-semiconductor-junction are considered in the calculation of the total channel current as well and are mainly dominated by the mismatch of the metal work function and the semiconductor HOMO level (p-type semiconductor). Tunneling and thermionic currents are considered to be the main current contributions at the metal-semiconductor-junction and are calculated via a 2D solution of the electrostatic potential and electric field within the channel area [3]. Parasitic source and drain resistances are considered as well. The model is verified with measurements on OFETs fabricated with small molecules (Fig. 1), implemented in Verilog-A, and currently tested for circuit design.

Low-frequency noise reduction in vertical MOSFETs having tunable threshold voltage fabricated with 60 nm CMOS technology on 300 mm wafer process

In this paper, DC and low-frequency noise (LFN) characteristics have been investigated with actual measurement data in both n- and p-type vertical MOSFETs (V-MOSFETs) for the first time. The V-MOSFETs which was fabricated on 300 mm bulk silicon wafer process have realized excellent DC performance and a significant reduction of flicker (1/f) noise. The measurement results show that the fabricated V-MOSFETs with 60 nm silicon pillar and 100 nm gate length achieve excellent steep sub-threshold swing (69 mV/decade for n-type and 66 mV/decade for p-type), good on-current (281 µA/µm for n-type 149 µA/µm for p-type), low off-leakage current (28.1 pA/µm for n-type and 79.6 pA/µm for p-type), and excellent on–off ratio (1 × 107 for n-type and 2 × 106 for p-type). In addition, it is demonstrated that our fabricated V-MOSFETs can control the threshold voltage (Vth) by changing the channel doping condition, which is the useful and low-cost technique as it has been widely used in the conventional bulk planar MOSFET. This result indicates that V-MOSFETs can control Vth more finely and flexibly by the combined the use of the doping technique with other techniques such as work function engineering of metal-gate. Moreover, it is also shown that V-MOSFETs can suppress 1/f noise ( of 10−13–10−11 µm2/Hz for n-type and 10−12–10−10 µm2/Hz for p-type) to one or two order lower level than previously reported nanowire type MOSFET, FinFET, Tri-Gate, and planar MOSFETs. The results have also proved that both DC and 1/f noise performances are independent from the bias voltage which is applied to substrate or well layer. Therefore, it is verified that V-MOSFETs can eliminate the effects from substrate or well layer, which always adversely affects the circuit performances due to this serial connection.

Comparative Study of a Single Inverter Bridge for Dual-Frequency Induction Heating Using Si and SiC MOSFETs

The induction surface hardening of parts with nonuniform cylindrical shape requires a multifrequency process in order to obtain a uniform surface hardened depth. This paper presents an induction heating high power supply composed by a single inverter circuit and a specially designed output resonant circuit. The whole circuit supplies simultaneously both medium- and high-frequency power signals to the heating inductor. An initial study is made to select the most appropriated topology for this application. The resonant output circuit is analyzed, and a design procedure is presented. The selected inverter operation is described and simulated. Simulations are experimentally verified on a 10-kW dual-frequency resonant inverter operating at 10 and 100 kHz using MOSFETs of silicon (Si) and silicon carbide (SiC) technology. A comparative study is presented based on the measurements of power losses and the energy efficiency of the inverter using both types of MOSFETs.

Threshold Voltage Instability in 4H-SiC MOSFETs With Phosphorus-Doped and Nitrided Gate Oxides

Threshold voltage instability was investigated for 4H-SiC MOSFETs with phosphorus-doped (POCl3-annealed) and nitrided (NO-annealed) gate oxides. Threshold voltage shift observed in the bidirectional drain current–gate voltage characteristics was evaluated using various gate voltage sweeps at room and elevated temperatures up to 200 °C. The threshold voltage shift was also studied after applying positive and negative bias-temperature stress. Two types of MOSFETs showed different instability characteristics, depending on gate biases and temperatures. These features were found to originate from the difference in trap density and trap location at/near the oxide/SiC interface and in the oxide. It is apparent that the oxide traps in phosphorus-doped oxides and near-interface traps in nitrided oxides are the main origin of the threshold voltage instability via capture and emission (in the case of oxide traps, only capture) of both electrons and holes.

MWCNT 가스센서의 전극 간극 변화에 따른 NOx 가스 검출 특성

Carbon nanotubes(CNT) has chemical stability and great sensitivity characteristics. In particular, the gas sensor required characteristics such as rapid, selectivity and sensitivity sensor. Therefore, CNT are ideal materials to gas sensor. So, we fabricated the NOx gas sensors of MOS-FET type using the MWCNT (multi-walled carbon nanotube). The fabricated sensor was used to detect the NOx gas for the variation of <TEX>$V_{gs}$</TEX>(gate-source voltage) and electrode changed electrode spacing=30, 60, 90[<TEX>${\mu}m$</TEX>]. The gas sensor absorbed with the NOx gas molecules showed the decrease of resistance, and the sensitivity of sensor was increased by magnification of electrode spacing. Furthermore, when the voltage(<TEX>$V_{gs}$</TEX>) was applied to the gas sensor, the decrease in resistance was increased. On the other hand, the sensor sensitivity for the injection of NOx gas was the highest value at the electrode spacing <TEX>$90[{\mu}m]$</TEX>. We also obtained the adsorption energy(<TEX>$U_a$</TEX>) using the Arrhenius plots by the reduction of resistance due to the voltage variations. As a result, we obtained that the adsorption energy was increased with the increment of the applied voltages.