MOSFET-only Voltage Reference Research Articles

An ultra-low power high-precision logarithmic-curvature compensated all-CMOS voltage reference in 65 nm CMOS

In this paper, a low-complexity resistorless high-precision sub-1 V MOSFET-only voltage reference is presented. To obtain an accurate output, a curvature-compensation technique is used, canceling its logarithmic temperature dependence regardless of the value of the mobility temperature exponent $$(\gamma )$$ . The circuit is realized in 65 nm CMOS technology and yields an output voltage of 574 mV, a temperature coefficient of 3.5 $$\frac{{{\text{ppm}}}}{{^\circ {\text{C}}}}$$ in the range of − 50 to 150 °C, a power supply rejection ratio (PSRR) of − 103 dB at 100 Hz, a line sensitivity of $$6\,\frac{{\upmu {\text{V}}}}{{\text{V}}}$$ in the supply voltage range of 1.3–3 V, a power dissipation of 650nW at 1.3 V supply, and an output noise of 1.7 $${\mu V}/\sqrt {{\text{Hz}}}$$ at 100 Hz. The total active area of the design is 0.03 mm2. This voltage reference is suitable for low-power low-voltage applications which also require high precision.

A 0.6 V 31 nW 25 ppm/°C MOSFET-only sub-threshold voltage reference

A low-power low-supply high-LR high-PSR MOSFET-only voltage reference is proposed in this paper. The proposed voltage reference is designed in the standard 0.18µm CMOS process. In the typical case, when the temperature sweeps from −20°C to 80°C, the simulation result shows that the proposed voltage reference achieves a temperature coefficient of 25ppm/°C. And the line regulation is as high as 0.067%/V, at room temperature. At the low frequency (<100Hz), a PSR of 44dB is obtained. The reference succeeds in working at the supply voltage as low as 0.6V, with the power consumption being 31nW. The proposed voltage reference occupies an area of 130µm ×55µm.

A 5.6 ppm/°C Temperature Coefficient, 87-dB PSRR, Sub-1-V Voltage Reference in 65-nm CMOS Exploiting the Zero-Temperature-Coefficient Point

This paper describes an MOSFET-only voltage reference realized in 65-nm CMOS featuring a temperature coefficient (TC) of 5.6 ppm/°C from -40 °C to 125 °C, a power supply rejection ratio of 87 dB from dc up to 800 kHz (and 75 dB at 1 MHz), a minimum supply voltage of 0.8 V, and a power dissipation of 13 μW. These attributes are achieved by exploiting the zero-TC point of an MOSFET and combining it with a novel curvature-compensation technique, an active attenuator, and an impedance-adapting frequency compensation scheme.

EMI resisting MOSFET-only voltage reference based on ZTC condition

Electromagnetic interference (EMI) can significantly degrades the performance of analog circuits, including voltage and current references, especially due to their limited power supply rejection. An EMI resistant MOSFET-only voltage reference is herein proposed, based on the MOSFET zero temperature coefficient (ZTC) vicinity condition. The ZTC condition is analytically derived through a continuous MOSFET model that is valid from weak to strong inversion, also a design methodology is presented. The final circuit is designed in a 130 nm process and occupies around 0.0075 mm$$^{2}$$2 of silicon area while consuming just 10.3 $$\upmu$$μW. Post-layout simulations present a 395 mV reference voltage ($$V_{REF}$$VREF) with a effective temperature coefficient ($$TC_{eff}$$TCeff) of 146 ppm/°C, for a temperature range from ź55 to +125 °C. A 4 dBm (1 $$V_{pp}$$Vpp amplitude) EMI source injected into the power supply, according to direct power injection standard [1], results in a maximum DC Shift and peak-to-peak ripple of ź1.7 % and 35.8 m$$V_{pp}$$Vpp, respectively. The proposed voltage reference has already been fabricated and is under preliminary measurements, presenting a maximum variation of 21 mV for a 600 mV minimum supply.